/> IC Plus has incorporated the Cadence OVM architecture and methodology into its SystemVerilog verification flow and significantly shortened its development time from months to only a few weeks. By adopting the Cadence solution, IC Plus standardized its verification process, dramatically improving production efficiency and predictability while achieving high-quality verification closure. The OVM, implemented in IEEE 1800 SystemVerilog, IEEE 1647 e and IEEE 1666 SystemC, is a market-leading advanced verification methodology.

The OVM, which Cadence co-created, comprises several advanced features, including interoperability, debugging, reusability and an easy-to-use verification model for testing. Its universal interoperability for SystemVerilog and reusable verification IP help facilitate the development and support of multi-language plug-and-play VIP. Debugging and reusability help maximize quality, productivity and predictability. The proven user-friendly model provides a simple platform for test creation.

“For an IC design company like IC Plus, which has made great investments in R&D, the process of debugging is critical since it affects time and resources during the design process,” said Albert Liu, R&D Vice President of IC Plus. “With the Cadence solution, we are able to not only set up a complete, automatic and systematic verification flow with less set-up time, but also to discover design bugs in the early stage, which in turn improves the quality of our products.”

“Today's IC design companies are striving to improve their design efficiency by simplifying and standardizing their verification processes as early as possible in the design stage,” said Willis Chang, General Manager, Taiwan WFO Operations at Cadence. ”We are very glad to see IC Plus reaping savings and benefits from Cadence technologies and the Open Verification Methodology. IC Plus is seeing first-hand the capability of the Incisive verification solution for high-performance verification.”