IAR Systems releases new version of IAR visualSTATE for high-integrity small embedded systems

IAR visualSTATE is a set of highly sophisticated and easy-to-use development tools for designing, testing and implementing embedded applications based on state chart diagrams. It provides advanced verification and validation utilities, and generates very compact C/C++ code that is 100% consistent with the system design. In addition, its tight integration with IAR Embedded Workbench® enables true state machine debugging on hardware, with direct graphical feedback at various levels of detail.

IAR visualSTATE has already proved popular with customers in all industries, but particularly in the medical and industrial control sectors due to its focus on the state machine paradigm to address high integrity requirements. Designs generated by IAR visualSTATE can already be found in such exacting and diverse applications as blood glucose meters, underwater breathing apparatus, coffee machines and office ventilation control.

There are virtually no restrictions on the type of modelling constructions that can be used for verification, and the tool includes a comprehensive set of optimizations that reduce runtime and memory requirements for the system designs. This latest release also features improved compliance to MISRA C:2004. The generated code in the readable code format has been more closely aligned with the MISRA C:2004 guidelines, and with the guidelines published by MIRA on MISRA C:2004 in the context of automatic code generation.

“IAR visualSTATE and the state machine paradigm have generated a considerable amount of interest for applications with high integrity requirements, and the improved MISRA C:2004 compliance makes it an even better proposition for safety critical applications,” commented Anders Holmberg, visualSTATE product manager at IAR Systems. “The IEC-61508 standard on functional safety, for example, explicitly recommends state machines as a design method to meet higher SIL levels.”

Also new to IAR visualSTATE 6.20 is the ability to exclude specified design regions from code generation: it is possible to mark state machine regions and individual states on any hierarchical level for exclusion from further processing. The developer then has the option to confirm during code generation, verification and validation whether the marked regions should be excluded or included. This feature can be used to create simple product differentiation, or to generate different debug scenarios for code generation, validation, and verification.

A comprehensive example code index gives short descriptions relating to each of the accompanying code and applications examples – this includes applications examples for several of our the most popular IAR KickStart Kit products, including those for STM32 and LPC2148.

By designing a system of state machines in IAR visualSTATE, the developer is able to use the formal verification feature to uncover issues or anomalies in their design that would be virtually impossible to cover in full by writing test suites; these can include dead end situations, unreachable parts of the design, inputs that are unused, and similar problems.