How to implement voltage, current, power, and temperature monitor design

Beyond protection, integrating data logging capabilities takes system reliability to the next level. This approach not only shields systems from damage but also provides engineers with critical insights into their performance and condition.

To achieve this, an integrated circuit with three input channels of the Analog-to-Digital Converter (ADC) and an ability to compare measured data and log the results obtained is essential. The SLG47011 from Renesas, a device with a four-channel 14-bit ADC, four-channel 16-bit digital comparator, and data storage capacity is well-suited for these tasks.

This article describes in detail how to implement voltage, current, power, and temperature monitor design.

GreenPAK design

Figure 1 shows an internal design of the monitor in the Go Configure software.

Figure 1. Go Configure schematic of monitor

The main function in this circuit is performed by the ADC, which processes three channels simultaneously with the help of the Sampling Engine block. Signals can be amplified through the PGA, which is used in this project for channel 2, designed to measure current. For channel 0 (voltage measurement) and channel 1 (temperature measurement), PGA is used in buffer mode. The Multichannel Digital Comparator sets the static threshold for each channel. When any of the measured values exceeds this threshold, a High-level signal appears on the corresponding output. The Digital Comparator cannot directly take data from the ADC. For this purpose, Data Buffer 0, Data Buffer 2, and Data Buffer 3 are used to store the current values of the measurement.

An important block of the SLG47011 is the Mathematical Core (Math Core), which allows performing arithmetic operations on the measured values. In this case, the Math Core is used to multiply voltage and current values to obtain the power value.

Red LEDs are employed to indicate abnormal events. Depending on the event that occurred, the corresponding LED lights up.

Overvoltage detection

If, for example, as given in the application note, there is a need to detect when the input voltage reaches 6V, a divider must be used. Because this voltage exceeds the 1.62V ADC reference voltage, a 5:1 divider is appropriate. The ADC input voltage for this overvoltage event, with this divider, is calculated as follows:

With the ADC Vref = 1.62V, the digital comparator static threshold #3 value is set to:

Figure 2 shows the overvoltage detection tested on the SLG47011.

Figure 2. waveform illustrating overvoltage monitor

This solution is universal and allows for the selection of a divider and a comparator static threshold to set any voltage value at which the protection is triggered.

Overcurrent detection

Overcurrent detection with a threshold equal to 5A is considered as an example. For this purpose, a 0.02Ω current sense resistor is used, on which, when a current of 5A passes, 0.1V drops. The PGA channel 3 is configured as a differential input with a differential amplifier with a gain of 4. For the differential mode, the gain is applied to the difference between IN+ and IN- with an offset of the ADC Vref/2, or at the ADC Vref = 1.62V, the offset is equal to 1.62/2 = 0.81V. Therefore, the digital comparator static threshold #0 value is:

Figure 3 shows the overcurrent detection tested on the SLG47011.

Figure 3. waveform illustrating overcurrent monitor

Overpower detection

Sometimes it is not enough to measure only current and voltage. It is also desirable to know the power at these current and voltage values, because they may be within the permitted range, but high dissipation power can lead to failure. The Mathematical Core provides a 16-bit result to be compatible with the data bus width. Therefore, when multiplying the 16-bit current and 16-bit voltage values, a 32-bit value is obtained, causing an overflow. To provide a 16-bit result compatible with the data bus width, multiplication should be followed by a cyclic shift operation. The Math Core has a user-defined right-shifting value feature. In this example, a shift to the right by 10 positions is used. This shift value was chosen to accommodate the maximum expected value of the multiplication result.

Given that a current in Data Buffer 0 is stored with an offset of Vref/2, or 8192 in the code, when multiplying this current by a voltage value, the offset (midpoint) must be subtracted. This ensures that when there is no current and voltage at the input, the power value is also zero.

For example, set the power threshold to 25W. This value can be obtained, for instance, at a current of 4.5A (static threshold = 11832) and a voltage of 5.5V (static threshold = 9270). Firstly, it is necessary to subtract the midpoint from the current value: 11832 – 8192 = 3640. To set the power threshold to 25W, it is necessary to configure the static threshold #1 value of the digital comparator as (3640 x 9270) >> 10 = 32951.

Figure 4 shows the overpower detection tested on the SLG47011. As can be seen from the waveform, neither the voltage nor the current reaches their thresholds, but the power does reach the threshold of 25W.

Figure 4. waveform illustrating overpower monitor

Overtemperature detection

Because the SLG47011 has a built-in Analog Temperature Sensor, it can be used to detect overtemperature. Consider, for example, a desired threshold of 100°C. According to the Analog Temperature Sensor specifications, the Temperature Sensor output voltage at 100°C is 0.5625V.

With the ADC Vref = 1.62V, the digital comparator static threshold #2 value is:

During testing, the stored result in Data Buffer 3, responsible for the sensor output, was read, and the value 0x1BF1 (7153) was obtained. This value is significantly below the threshold and is equivalent to approximately 0.707V and 25°C, respectively. Therefore, in this case, the OUT2 of the digital comparator has a LOW voltage, signifying the absence of the overtemperature. The flexibility of the SLG47011 allows for setting any threshold and detecting any temperature anomalies.

Data logging

The SLG47011’s Data Buffers can also be used for data logging. In this article, Data Buffer 1 performs this function. At the moment of switching on and until the overpower occurs, it contains a zero value. However, when the overpower event happens, the HIGH-level signal from the comparator OUT1 is fed through the 2-bit LUT1 to the LOAD input of the buffer. With this signal, the buffer writes abnormal power values from the Math Core output. Users can read this buffer data via I2C or SPI. Specifically, bytes 0x2224~0x2225, contain the result value of the buffer and based on these data, can judge the occurrence of the overpower event. If the read data value is above the static threshold value 32951, it indicates that the overpower has occurred.

Figure 5 shows the Go Configure Tool for reading Virtual Inputs, namely, Data Buffers value during overpower.

Figure 5. data buffers value during overpower in Go Configure tool

When the user reads the buffer and sees that an abnormal event has occurred, they can reset this value using the button “Reset Logger.” To filter out switch bouncing, a Delay macrocell DLY4 is used.

Thanks to the versatility of the SLG47011, it is possible to log current, voltage, or temperature instead of the power given in this design.

Anti-aliasing filters

Low-pass filtering is essential to eliminate any frequency components (harmonics) within the analog signal that surpass the Nyquist frequency. When frequency components in the analog signal exceed the Nyquist frequency, an undesired phenomenon called aliasing occurs.

Resistor R2 and capacitor C3 form a filter with a cutoff frequency equal to   and are intended to prevent aliasing when voltage is measured. Resistors R7, R8, and capacitor C4 form a filter for current measurement channel with a cutoff frequency equal to

PGA offset cancellation

The SLG47011 has built-in system calibration – specially designed customer calibration to simplify some differential mode measurements. In this design to eliminate PGA offset error for the current measurement channel the system calibration is used.

PGA channel 2 serves as the calibration channel. For this channel, the PGA settings must be configured the same as for channel 3, which is the main measurement channel. Additionally, it is recommended to shorten the inputs of the offset compensation channel and connect them with the same common-mode voltage as the measurement channel. Note that not all ADC channels have a calibration function. The compensation channel must either be channel 0 (for a pair of channels 0 and channel 1) or channel 2 (for a pair of channels 2 and channel 3). The compensation is activated by setting the System calibration register for the pair channel 0,1 or channel 2,3, and by applying a pulse to the ADC Calibration input.

To initiate the ADC calibration and conversion, it is necessary to provide a delay, which is achieved using a 100ms delay (DLY4). CNT5 set calibration period and after 1s starts calibration. CNT/DLY6 (One Shot) set conversion period.

Increasing accuracy when measuring current

The above current measurement is quite accurate. However, this measurement does not consider the sense resistor error and PGA gain error. With the SLG47011, it is possible to further improve the accuracy of current measurement by compensating for these errors. This makes it impossible to monitor power, as the Mathematical Core need to be used to compensate for the error. However, in this case, the current will be monitored with higher accuracy.

Because in this application the current is measured in differential mode and the gain is applied to the difference between IN+ and IN- with an offset of the ADC Vref/2, before starting the compensation, subtracting the midpoint from the measured value is essential.

To implement the compensation, the real gain and sense resistor value must be measured by the user. Then, their errors must be calculated and added to determine a rational number, which is essentially a correction factor. The Math Core adjusts that error by multiplying the measured current value by constant K and right shifting the result. Right shifting by N bits is equivalent to division by 2N. If K is set to 32768 (215) and the right-shifting value is set to 15, it is equivalent to multiplying the measured result by a factor of 1. So, no input data manipulation is being conducted. However, using this formula, by changing the K value, the input data can be trimmed to compensate for the PGA gain error and sense resistor error.

For example, if after measuring the real gain error and sense resistor value, a correction factor of 1.03 was determined, then the constant value K will be: 32768 × 1.03 = 33751. Then this constant K multiplies with the measured current value and shifts the result to the right by 15. The resulting value will contain the error-compensated current value.

Conclusion

This article explores how the AnalogPAK SLG47011 can be used to monitor current, voltage, power, and temperature. Its four-channel 14-bit ADC ensures precise measurement of these signals, while the built-in calibration function improves accuracy by cancelling PGA offset. The device’s Mathematical Core enables calculations, such as determining power, directly within the system. Additionally, the SLG47011 supports data logging, all within a compact 2.0mm x 2.0mm package.