Tanner EDA Releases HiPer Silicon v15.23

24th September 2012

Tanner EDA

ES Admin

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Tanner EDA has released version 15.23 of its full-flow analog and mixed-signal design suite: HiPer Silicon. The addition of HiPer Simulation AFS to version 15.23 gives designers added capabilities for front-end design flow, including schematic capture, dual circuit simulators and waveform probing.

HiPer Silicon version 15.23 includes Tanner Analog FastSPICE, which integrates the Berkeley Design Automation Analog FastSPICE Platform with Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyser. With HiPer Simulation AFS, two Spice simulators deliver the ultimate in performance and productivity, even for large netlists. T-Spice provides fast, accurate analysis while T-AFS delivers accuracy with runtimes 5x to 10x faster than traditional Spice simulators, on a single core. Users can drive the T-AFS simulator directly from S-Edit, getting the speeds and accuracy necessary for nanometer design. Simulation results are displayed automatically in W-Edit for viewing, measuring, and analysing interactively.

As always, Tanner EDA offers a free 30-day evaluation.

Version 15.23 also adds new TCL commands to S-Edit, supporting greater functionality. And T-Spice now supports the HiSIM-HV model. Integration with Berkeley Design Automation transient noise analysis capability allows users to simulate realistic device noise effects for all circuits, especially non-periodic circuits such as sigma-delta ADCs and frac-N PLLs.

“With the T-AFS capability in version 15.23, Tanner EDA now offers the fastest, most productive and robust front end analog design package on the market,” said John Zuk, vice president of marketing and business strategy at Tanner EDA. “Users can now verify complex analog and RF circuits with nanometer Spice accuracy while still taking advantage of Tanner EDA’s industry-leading price-performance.”