ASSET ScanWorks is first to offer validation tools for new Intel® microarchitecture codenamed Haswell

According to Intel, microprocessors based on the microarchitecture codenamed Haswell and accompanying chipsets will be a key step toward achieving the company's UltrabookT vision of ultra thin, light, responsive and secure laptops and other types of designs. Crucial to achieving this vision will be the performance of the high-speed serial input/output buses that connect processors and chipsets to other devices on a circuit board. When bus speeds exceed approximately 5 gigabits per second (Gbps), as they will on Intel's future designs, they become super-sensitive to capacitive coupling effects. This means that legacy testers like oscilloscopes and logic analyzers must compensate for the effects that result from placing a probe on a high-speed bus to verify its performance. In many cases, the capacitive effects of probing can invalidate test results. Some external testers have attempted to overcome these difficulties by resorting to simulation or higher-order mathematics, but these techniques only generate a projection of the actual signaling on the bus.

Over the last seven years, ASSET has collaborated with Intel to overcome these shortcomings and to empower design and test engineers with advanced validation and test tools. Because ScanWorks is a non-intrusive, software-based tools platform, it can use the instruments embedded in Intel's chips to perform validation and test. The reports ScanWorks provides engineers are a more accurate reading of the signal integrity on an I/O bus than are the results from external, intrusive testers.

ASSET's new tool - ScanWorks High-Speed I/O for Intel® Architecture based on Intel® CoreT processor family - capitalizes on Intel's embedded instruments intellectual property. ASSET is leveraging the success that ScanWorks has achieved in the Intel server marketplace by enhancing its capabilities and migrating it to the desktop and mobile markets. The new tools provide advanced diagnostics, bit-error-rate (BER) testing and margining for the Direct Media Interface, PCI Express Graphics and DDR3 I/O buses. ASSET is a key third party vendor to Intel.

Intel is not only investing in the components needed to build the best possible computation and communication devices of today and tomorrow, we are also investing in on-die silicon capabilities and tools to test and validate the platform, said John Barton, vice president of the Intel Architecture Group and general manager of Platform Validation Engineering for Intel Corporation. By working with a leading tools vendor such as ASSET, the benefits of our tool investment can be extended beyond Intel's labs and into the hands of the designers and manufacturers requesting these enhanced capabilities through ASSET's ScanWorks tools suite.

Tim Caffee, ASSET's vice president of board validation, said: Due to the complexities of next-generation buses and their high speeds, designers must address a myriad of signal integrity challenges and, in the end, they must verify that all of the high-speed I/O buses meet or exceed their operational expectations. With this next-generation tool from ASSET, designers and test engineers can rectify problems long before a design moves into volume manufacturing. Failing to identify deficiencies during design would involve much greater expenses later after the design has moved into volume manufacturing.