Cooperation between GOEPEL electronic and DMP enables new Test Strategies for x86 System-On-Chip

“Due to their high integration level, VORTEX circuitries smooth the way to develop highly compact assemblies, controlled by a fully x86 compatible embedded PC, which have introduced problems in testing due to their BGA packaging”, explains Thomas Wenzel, GOEPEL electronics’ managing director of the JTAG/Boundary Scan Division. “We were able to solve these problems using our VarioTAP technology, i.e. new tools to ensure test quality during prototyping and in the production are available worldwide for all VORTEX customer projects”.

“The customer support in testing boards with VORTEX single-chip PCs is as important as advising in the design-in process”, says Gary Cheng, DMP’s Product Manager of the SoC Division. “That’s why we look forward to offer a completely new test strategy through the cooperation with GOEPEL electronic. Design and test moving together even closer.”

The VORTEX® series includes several complex system-on-chip(SoC) ICs with up to 720 BGA pins. A complete x86 architecture incl. Northbridge and Southbridge as well as nearly an entire periphery are integrated in the chips. Via the standard debug port VarioTAP® converts the x86 processor into a native design embedded test and programming controller. In addition too the Boundary Scan (IEEE 1149.x), the strategy referred to as Processor Emulation Test (PET) is currently the most modern method within the area of embedded test access technologies, enabling the functional at-speed test of all bus and communication interfaces of the VORTEX, such as USB2.0, LAN, IDE, COM, DDRII, ISA, PCI etc at chip, board and system level.