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The newly ratified IEEE 1149.7 is a complementary superset of the IEEE 1149.1 standard, which defines the standard test access port as well as boundary-scan architecture for test access ports. This standard also is used for application development, especially in the areas of developing and debugging software for complex systems (commonly referred to as JTAG for Joint Test Action Group which is the group that defined the standard).

The IEEE 1149.7 standard is intended to take the embedded industry to the next level of boundary scan debug and test support. While adding substantial functionality to the existing standard, the 1149.7 remains fully backward compatible with 1149.1. This allows a board or system that integrates chips or cores supporting either standard to be amenable to the same test or debug procedures. Specific benefits include:

* Reduced pin operation – IEEE 1149.7 provides a two-pin operation instead of the four-pin operation required in IEEE 1149.1. Fewer pins means lower cost and the ability to provide more functional output at the pin interface, which prevents more complex modes of operation such as pin multiplexing or the addition of costly pins.
* Multicore and multiprocessor support – A new system-level bypass capability simplifies and shortens the scan chain in a multiprocessor system. This provides faster access to a specific device in the system, which can improve the overall debug experience for these complicated system topologies.
* Power control – A standard set of protocols included in IEEE 1149.7 provides the ability to control debug logic power consumption in the system. This upgrade has only one “always on” state and provides four selectable power modes to enable low power devices for mobile applications.
* Advanced topology support – In addition to the standard serial topology, IEEE 1149.7 includes support for star topologies. This simplifies the physical inter-device connections for complicated multi-chip modules and stacked dies.

The IEEE 1149.7 standard contains a unique combination of reduced-pin debug/test interface capability as well as a next-generation feature set including concurrent debug and instrumentation over the same pins, multi-drop capability, a built-in chip select mechanism, download specific modes of operation, chip level bypass operations and support of custom technologies.

“The IEEE1149.7 standard allows us to reduce the test interface pin count to two pins, down from four or more on devices currently using the 1149.1 interface, while at the same time adding more advanced capabilities to Freescale’s embedded products,” said Rob Oshana from Freescale Semiconductor’s Networking and Multimedia Group and chairman of the IEEE 1149.7 working group. “In addition, the IEEE working group plans to provide support for this next generation technology through a number of embedded tools vendors.”

Freescale’s adoption of the IEEE 1149.7 standard is complementary to its leadership position in IEEE-ISTO 5001 (Nexus), which is a best-in-class on-chip debug technology. A primary Nexus goal is to provide the best possible debug feature set while minimizing the required pin-count and die area. This aligns well with the goal of 1149.7 reduced pin debug access. The Nexus standard also is designed to be processor and architecture independent, supporting both multicore and multiprocessor designs. This goal also aligns well with the capabilities and features of 1149.7

IEEE-ISTO 5001 (Nexus) has added reduced pin-count support in two dimensions: high-speed serial capability for high performance processors and IEEE 1149.7 support for lower cost implementations,” said Rich Collins, the Hardware Technical chairman for Nexus. “Adopting the IEEE 1149.7 standard with its two-pin interface provides this low cost transport capability while maintaining compatibility with legacy IEEE 1149.1 interfaces and IP.