Forte Renews License for Verific Design Automation Software

The license was originally issued in 2006 to Arithmatica Ltd., a company acquired by Forte last year. At that time, Verific’s Verilog parser and register transfer level (RTL) elaborator were integrated with CellMath Designer to provide tighter integration flow for Verilog users and easy-to-use syntax to specify datapath structures.

“We’re delighted to be working with Forte as it enhances CellMath Designer’s value to the engineering community,” says Michiel Ligthart, Verific’s chief operating officer. “Forte is extending its powerful brand into a new market segment through product excellence and quality of results.”

Project teams use CellMath Designer as an optimization step prior to logic synthesis to reduce area, improve performance and lower power consumption for datapath-intensive design blocks. Using CellMath intellectual property (IP), CellMath Designer combines advanced synthesis techniques with datapath architectures to reduce circuit area and power and for circuit speeds unachievable through other means. CellMath Designer works in conjunction with general logic synthesis products and utilizes existing RTL code, synthesis scripts and technology libraries to allow designers to quickly improve results.
Concludes Sean Dart, Forte’s president and chief executive officer: “Verific’s reputation for solid product offerings and strong customer support are well earned. We’ve been impressed with Verific’s willingness to work with us through the transition and its commitment to making CellMath Designer a ‘must-have’ datapath synthesis tool.”