Forte Unveils Cynthesizer Ultra, Next-Generation High-level Synthesis

Both products, available now in volume shipments, simplify hardware and electronic system level (ESL) design to improve circuit performance and reduce chip costs.

“Cynthesizer and Cynthesizer Ultra are redefining the way hardware is designed and making it fun for hardware designers again,” says Brett Cline, Forte’s vice president of marketing and sales. “The Cynthesizer product family raises the abstraction level of design by automating mundane tasks while providing the quality of results, power reduction and support for the overall ESL design flow required for cutting edge hardware design.”



Introducing Cynthesizer Ultra

Forte’s CellMath technology and patented intellectual property (IP) offers improved quality of results by creating better datapath components. Integrating Cynthesizer with CellMath Designer™ datapath optimization and CellMath intellectual property (IP) gives design teams a way to create better designs using more optimized building blocks faster.

Cynthesizer Ultra uses CellMath Designer as an embedded datapath optimization capability to create datapath components as needed for use in the high-level synthesis process. These products work together to perform automated design-space exploration that will search for the best set of components for each individual design. With these techniques, Cynthesizer Ultra improves power consumption and timing, and reduces area by up to 40% compared to previous versions.



Cynthesizer Ultra adds access to the CellMath IP library including advanced, floating point functional units used by leading-edge graphics companies. This IP can be accessed directly from SystemC through an automated flow.



Features for Improved Design, Verification, Quality of Results

Cynthesizer includes a new schedule analysis detail view. This allows designers to converge on their final design more quickly by giving them specific direction to correct or improve areas of the design that may not meet their quality of results (QoR) goals. High-level synthesis automatically builds the design “schedule” that includes creation of the datapath and finite state machine (FSM) to meet a given set of user-directed and/or hardware design constraints. When these constraints cannot be met, Cynthesizer gives the user specific direction for further input, reducing the design time needed.



Cycle Accurate simulation technology improves verification performance. Using Cynthesizer’s automated methodology management software, designers can quickly execute behavioral simulations, high-level synthesis and utilize Cynthesizer Cycle Accurate simulation to accelerate the output RTL implementations. With speeds up to 20x over traditional register transfer level (RTL) simulation, designers have a high-performance, cost-effective and integrated solution to meet their verification challenges.



Cynthesizer also includes updates to its CynWare IP interface library. Designers can use its extensive pre-verified library and new faster memory interface support for greater flexibility, better performance and lower power.



Additional features and optimizations further reduce circuit power utilization and improve tool runtime and capacity.