Floorplanning EDA tool from Teklatech looks set to revolutionize SOC power management

The new tool combines powerful power signature analysis and automated power peak reduction providing better results, improved yield and a more efficient solution for a wide range of SoC applications, including multimedia, DSP, wireless, networking and mobile.

Until now, semiconductor companies have had to solve power related issues at the physical level, incurring significant design risk and overhead. FloorDirector reduces dynamic IR drop and supply noise by intelligent power shaping, flattening power peaks, thus improving signal and power integrity. The tool enables semiconductor design teams to address dynamic power issues, optimizing their SoCs for low power and minimizing supply noise in early design phases, with minimum risk and cost. Comments Founder and CEO, Dr Tobias Bjerregaard: “FloorDirector™ produces a 51% reduction in power peaks over baseline EDA flows from major vendors”

In today's SoC designs, dynamic power peaks are of increasing significance. They can lead to ground and power bounces, impairing signal integrity and noise margins, and forcing conservative constraints on SoC implementation.

Voltage drops and supply noise will lead to unpredictable signal integrity, power integrity and timing effects and may cause a silicon failure. Mixed-signal SoCs encounter additional challenges due to noise coupling between digital and analog parts which degrades RF performance.

The FloorDirector floorplanning engine analyzes the dynamic power signature of every system block and identifies initiators of critical voltage drop chains in the design. Utilizing novel power shaping techniques and statistical clock timing analysis, FloorDirector provides system-level IR drop solutions while maintaining scalable clock-level synchronization. This allows engineers to floorplan a chip for optimal power peak flattening, leading to reduced dynamic IR drop and hence improving overall signal and power integrity.

“Teklatech is sharply focused on meeting the difficult challenges of the semiconductor industry moving into the nanometer era”, adds Bjerregaard, “We strongly believe we can drive the power/cost curve of designs at 90 nm and below, enabling companies to eliminate costly silicon re-spins and achieve faster time-to-market, leading to smaller, faster and more profitable semiconductor products.”

Teklatech formally unveiled its new EDA software tool at DATE show in Munich, demonstrating its benefits with real-world, MPSoC designs.