Arteris FlexNoC Network-on-Chip Technology Designed into Majority of Mobile SoCs

The Arteris FlexNoC interconnect IP solution has been used in such designs since 2007 by market leaders including Qualcomm, Texas Instruments, HiSilicon and other vendors that provide leading SoCs for the highest volume and fastest growing mobility markets.



After calculating the market share positions of those companies and adding the market share from other Arteris mobility customers, Arteris has determined that its FlexNoC interconnect IP solution is in more than 60 percent of application processors and LTE modems by number of SoC projects.



“The Forward Concepts survey titled “Cellphone & Tablet Core Chip Markets '13” identifies Qualcomm and Samsung as the dominant players in smartphone and tablet core chip markets segments,” said Will Strauss, president of Forward Concepts. “Companies that establish dominant market share at these customers in their respective IP categories will not only see design wins but increasing SoC volume growth. Arteris is staking its claim as one of the companies helping leaders to improve upon their success in bringing market dominating application processors and LTE modems into popular systems and devices.”



“Arteris has achieved over 60% project market share in mobility SoC projects by working with market leaders, over the last 3-5 years, to improve their ability to deliver more SoCs with improved technology performance and better gross margins. We are happy to report that the shift to network on chip interconnect IP tool kits for system-on-chip innovation continues to gain momentum,” said K. Charles Janac, President and CEO of Arteris. “The Arteris FlexNoC Network on Chip interconnect IP technology is one of the most significant SoC productivity innovations of the current decade based on technology results and market adoption.”



Arteris FlexNoC is the leading interconnect fabric IP chosen because it provides chips design teams with key advantages:



-Accelerated time-to-market through shorter design cycles

-Ability to produce multiple chip versions based on a common SoC platform

-Greater interconnect speeds resulting in improved performance

-Reduced die size and cost of chips

-Reduced power consumption due to advanced clock and power management features, and fewer gates and wires