Extraction solution certified for TSMC 16nm FinFET

At 16nm, there are new modeling challenges, including the introduction of FinFET 3D device structures, with more complex parameters for parasitic capacitance and resistance. These challenges require the highest accuracy in signoff extraction. Quantus QRC Extraction solution is able to meet these challenges using its robust modeling infrastructure to deliver the highest accuracy models, and produce the smallest netlist to enable faster simulation and characterisation runtimes.

Suk Lee, Senior Director, Design Infrastructure Marketing Division, TMSC, comments: "The certification of Quantus QRC Extraction solution by TSMC is the result of close collaboration between both companies’ R&D teams to accurately model complex parasitic effects to address the new challenge of FinFET devices. We are delighted to see Quantus QRC Extraction delivers the solution for FinFET designs that meet TSMC’s certification requirements and will continue our collaboration with Cadence on future technologies.”

“With Quantus QRC Extraction solution, our customers can reduce their design closure turnaround time by removing the extraction performance bottleneck in the digital and custom/analog electrical signoff flow. With the introduction of this new extraction solution and certification by TSMC at 16nm FinFET designs, Cadence now offers a significantly differentiated solution for digital, and custom/analog designs,” adds Anirudh Devgan, Senior Vice President, Digital & Signoff Group, Cadence.