EVE Enhances Emulation Platform with Superior Debugging Capabilities

This capability, never before implemented in standard field programmable gate array (FPGA)-based emulation systems, closes the gap with application specific integrated circuit (ASIC)-based emulators.

Through a feature called Combinational Signal Access (CSA), ZeBu (for Zero Bugs) users now can generate complete waveforms of their design, enhancing productivity and lowering the cost of ownership. Using CSA, values of any register transfer level (RTL) net, register or memory in the design are available quickly with unlimited trace depth and without embedding instrumentation or recompiling the design.

“With CSA, tracing a design bug in large designs of hundreds of millions of ASIC-equivalent gates is no longer a tedious, uncertain and, ultimately, ineffective exercise,” says Lauro Rizzatti, general manager of EVE-USA. “Early users of this new ZeBu capability confirmed that design bugs can be pinpointed in just a few hours, if not minutes, on the largest designs.”

CSA works in one of two modes: on-line, when waveforms are generated while the model is running on the emulator; and off-line, when waveforms are generated after the emulation run, enabling the emulator to be used for other applications. The off-line waveform generation process can be done on the user’s computer and accelerated for very large designs through a proprietary multicore technology.

CSA comes as a standard component to the ZeBu family. It is available now and, initially, works with zFast, ZeBu Fast Synthesis used with ZeBu emulation systems. EVE will demonstrate CSA at the Electronic Design and Solution Fair (EDSFair 2011) in Booth #401 January 27- 28 at the Pacifico Yokohama in Kanagawa, Japan.

ZeBu-Server combines the fastest speed of execution with the smallest footprint, and is installed in the verification flow at five of the top six semiconductor companies. It is used for SoC hardware verification and software development to shorten time to tapeout, improve product quality and eliminate costly respins, while shortening software development time ahead of silicon.