Design
EU’s FP7 SATURN project delivers UML/SysML-based hardware/software co-design solution based on Artisan Studio
Artisan Software Tools has announced the first technology solution to emerge from the European Union’s Framework7 SATURN project – a UML/SysML-based hardware/software co-design environment based on Artisan Studio.
“BDeveloped in conjunction with the University of Paderborn (Germany), the UML/SysML-based hardware/software co-design solution utilizes an enhanced SysML profile linked to a SystemC code generator for Artisan Studio. This generates executable SystemC which is then translated into VHDL for execution in an FPGA. The generated code can also be used to simulate systems in the Artisan EXITE ACE environment, including hardware simulation. This co-design and code generation solution has been fully evaluated using two complex, industrial proof-of-concept cases studies – a smart camera system and an outdoor broadband wireless telecommunications system. These initial case studies resulted in 56% and 58% automatic code generation respectively, with the simulation behaving as the final FPGA implementation. With the added benefits of the modeling environment managing all of the code and the documentation, this technology offers great promise.
“SATURN is just one of several European Union and standardization projects that we are actively involved with,” James B. Gambrell, President and CEO of Artisan Software Tools. “Our involvement in SATURN will enable us to both further strengthen Artisan Studio’s position as a leading UML/SysML development tool and increase our market share in verification infrastructures based on the system requirements, co-simulation, integration and test tools acquired as part of Extessy’s recent merger with Artisan. I am delighted to see this project bear fruit with this initial delivery. The results already show great promise and future benefits for organizations involved in hardware-software co-design.”
This first phase of the project concentrated on hardware (FPGA) modeling. In the next phase, the environment will be expanded to offer target processor simulation for software and the simulation of the SystemC in the EXITE ACE environment. The project will also use the MARTE profile for Formal System Design (ForSyDE), and develop a HetSC profile in conjunction with the University of Cantabria which will aid formal verification of developed systems. This will be evaluated using proof-of-concept case studies and is expected later in 2010.