Environment speeds PCB timing closure by up to 67%

This is an increasingly important capability as data rates increase and supply voltages decrease in today’s advanced protocols, including DDR3/DDR4, PCI Express, and SATA. TimingVision environment is ideal for any PCBs that include advanced high-speed interfaces and is especially suited to PC, tablet, smartphone and cloud data centre infrastructure applications.

TimingVision environment uses an embedded timing engine to analyse the entire interface structure and develop timing goals to help designers visualise real-time delay and phase information directly on a canvas. This greatly reduces manual editing, overall implementation time and designer effort. When combined with the Cadence Sigrity power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.

TimingVision environment, which provides dynamic feedback on the active and related signals during edits on the design canvas, features Auto-interactive Phase Tuning, to compensate both static and dynamic phase constraints on a selected set of differential pairs, and Auto-interactive Delay Tuning, to compensate for propagation delay, relative propagation delay and total etch length constraints specified in the physical design on a selected set of signals such as a byte lane.

AJ Incorvaia, Vice President, R&D, Cadence, comments: “Cadence is in a unique position to address all high-speed IP implementation and verification needs, from chip to end product. With the introduction of TimingVision environment, PCB designers now have a proven and highly efficient solution to meet increasingly complex timing closure challenges.”

TimingVision environment, along with the auto-interactive routing environment, is available now as part of the Allegro PCB High-Speed Option.