Engine drives development time reductions

Now, customers can design and implement at higher levels of abstraction for significantly faster design cycles to meet next-gen design opportunities.

The Spectra-Q engine features faster algorithms and allows for incremental design changes without needing to perform a full design compile. The engine also features a hierarchical database that enables users to preserve placement and routing information of IP blocks while making changes in other parts of the design. This helps ensure stable designs, eliminates unnecessary timing closure efforts and reduces compile times.

The engine also includes a common high-level design compiler for better quality of results and tighter integration between the Quartus II software and a variety of different front-end tools.

Built on top of the Spectra-Q engine is an industry first platform design tool called BluePrint, which allows designers to perform architectural exploration and assign interfaces with greater efficiency. The tool reduces design iterations tenfold by allowing designers to explore and create legal IO placements up-front with real-time fitter-checking. The tool also includes a clock and core planning feature that greatly reduces the number of design iterations needed for timing closure.

The Spectra-Q engine also fast tracks design entry for software, hardware and DSP designers alike. With multiple versatile design flows, designers can target FPGAs with greater efficiency in the language or design environment they prefer. In addition to providing support for the latest HDL languages, the engine is designed to support Altera’s A++ Compiler for High Level Synthesis (HLS) to create IP cores from C or C++ which significantly boosts productivity through faster simulation and IP generation.

Altera has also concurrently released its Quartus II software version 15.0. With this latest release, customers can take advantage of Altera’s proven software tools which deliver industry-leading compile times. Altera continues to expand its optimised IP offering with the latest standard-based cores to enable maximum design productivity. The Quartus II software v15.0 introduces Hybrid Memory Cube and HDMI 2.0 MegaCores for the company’s Arria 10 FPGAs and SoCs. The portfolio also includes an upgrade in features and device support for the company’s popular JESD204B core to update Arria V support to 9.255Gb/s as well as Cyclone V support up to 5Gb/s. IP debug toolkits for external memory interfaces and PCI Express are also available to help designers rapidly prototype and expedite qualifications with additional access points to perform test and debug on IP cores.

“As FPGAs and SoCs deliver dramatically increased capabilities with multi-million logic element devices, support for hundreds of interface protocols, and hardened functional blocks, the productivity of software design tools must scale at a much faster pace than just logic element counts,” said Alex Grbic, Senior Director, Software and IP Marketing, Altera. “The Spectra-Q engine is a game-changing combination of software technologies that dramatically accelerates the design process by reducing designs iterations, while continuing to deliver the industry's fastest compile times.”

The Spectra-Q engine is available as an early access programme. Customers interested in participating in the programme should contact their local sales representative. Both the Subscription Edition and the free Web Edition of the Quartus II software v15.0 are now available for download on Altera's website.

Altera’s software subscription programme consolidates software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera edition, and a full license to the IP Base Suite, which includes Altera’s most popular IP cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.