Emulation system targets functional verification of SoC designs

The Veloce 2 emulation platform is a hardware emulator that reduces project schedules and costs by delivering high-performance simulation acceleration, virtual emulation, and traditional in-circuit emulation of complex SoC designs. The Veloce 2 platform achieves these benefits through a emulation-on-chip architecture and best-in-class software and hardware technologies, delivering fast compiles, full debug visibility, and advanced memory modeling.

“Our primary goal is to create an environment of technology innovation that is recognized as an internationally competitive high-tech research institute,” said Sun Chongli, executive vice president, Shanghai ZhangJiang Institute. “Delivering such a goal requires investments in best-in-class solutions and products, which is why we have chosen Mentor as a partner for hardware emulation technology with the acquisition of their world-renowned Veloce 2 emulator. Using Veloce 2, we plan to train 300-500 engineers every year in China in SoC verification using best practices. With Mentor’s leadership in emulation, we believe we can fulfill our desire to have the best SoC verification experience for our users and clients in China.”

“We are very proud to announce our partnership with the Shanghai ZhangJiang Institute, delivering the latest-generation technology in hardware emulation with our highly advanced Veloce 2 system,” said Eric Selosse, vice president and general manager, Mentor Emulation Division. “The complexity of verifying SoC designs has made emulation a necessary part of the electronic system verification process.  Because Mentor is deeply rooted in delivering verification technology from the system to the RTL level, we anticipated how SoC complexity would make emulation imperative, and built our Veloce 2 platform to scale to the growing need for comprehensive system-level verification.”