EMIR solution aims to create fastest path to design closure

5th August 2014

Staff Reporter

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A transistor-level EMIR solution, designated the Voltus-Fi Custom Power Integrity Solution, has been introduced by Cadence. Delivering foundry-certified, SPICE-level accuracy in power signoff, the solution aims to create the fastest path to design closure. Enabled by the company's Spectre Accelerated Parallel Simulator signoff SPICE simulation, the company claims that the solution provides best-in-class accuracy at the transistor level, thereby meeting complex manufacturing specifications at advanced nodes.

Key capabilities of Voltus-Fi include the company's patented voltage-based iteration method, which requires a smaller memory footprint and runs faster than the industry’s traditional current-based iteration method. The solution also allows for the full integration with the Cadence Virtuoso platform, providing a single design flow that improves designer productivity in analog and custom block EMIR signoff. The company's Quantus QRC Extraction Solution leverages transistor-level parasitic extraction, while the Cadence Spectre Accelerated Parallel Simulator and Cadence Spectre Extensive Partitioning Simulator aids transistor-level simulation.

The integration between Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution provides a seamless flow for advanced analog/ mixed-signal power signoff for designs with mixed transistor-level and cell-level blocks. Quick analysis, debugging and optimisation is delivered through visualisation of EMIR results.

“The lowest possible power is imperative to customers of our iCE40 and ECP5 FPGA product families, and Voltus-Fi Custom Power Integrity Solution ensures that we achieve exceptionally accurate transistor-level results while minimizing power consumption,” said Sherif Sweha, corporate VP of research & development at Lattice Semiconductor. “As Lattice continues its focus on mobile and mobile-influenced markets, we are also using Voltus IC Power Integrity solution at the cell-level for a complete, best-in-class power signoff solution that optimizes mobile devices.”

“With the Cadence Voltus-Fi Custom Power Integrity Solution, customers can now achieve the most accurate EMIR results for transistor-level blocks, from analog IP blocks to embedded memories, in their Virtuoso environment,” said Anirudh Devgan, senior vice president, Digital & Signoff Group, Cadence. “In addition, Voltus-Fi Custom Power Integrity Solution generates accurate IP-level power-grid models for transistor blocks. This enables customers to then run Voltus IC Power Integrity Solution to achieve complete, full-chip SoC power signoff at top level, which results in the fastest path to design closure.”