Easily debug designs combining MIPS & ARM CPUs

TRACE32 now supports MIPS Release 6 CPUs including the new M-class M6250, the first embedded-class MIPS CPU to incorporate the MIPS On-Chip Instrumentation (MIPS OCI) flexible on-chip CPU debug architecture. Companies can use MIPS OCI to ensure the lowest possible risk and impact on their debug process for highly-integrated heterogeneous SoCs. 

“For many years, Lauterbach has supported the popular MIPS architectures and cores," said Norbert Weiss, International Sales and Marketing Manager, Lauterbach. "With TRACE32, the developers that are creating products around MIPS have access to a full range of debug functionality, from bootstrap code to interrupt routines and drivers. Now developers can even use TRACE32 for designs which combine the MIPS and ARM architectures.” 

Lauterbach debug tools have become a favourite with many hi-tech engineers, and the company is recognised for both engineering excellence and exceptional technical support. Lauterbach tools support all the major families of microprocessor cores, covering products from 75 silicon companies. The quality and capability of Lauterbach tools enable engineering teams to develop robust code whilst minimising development time lost to debugging.

TRACE32 enables simultaneous debug of the multiple CPUs in a design with ‘mixed mode’ trace streams. Users can view the interleaved results in a single trace window, with a system-level timestamp to help align the streams. Extended trigger logic enables cross-triggering between the CPU trace logic to make it even easier to debug processor interdependencies. With its TRACE32 debugger products, Lauterbach provides development tool support for a range of MIPS processors. 

“Because so many of our customers use Lauterbach tools, it’s important that TRACE32 works with MIPS OCI,” said Jim Nicholas, vice president of MIPS business operations, Imagination. “This new development continues to extend the MIPS ecosystem, offering designers an even wider choice of leading development tools. The great amount of focus we are putting on continued development of the MIPS roadmap and ecosystem is enabling potential customers to consider using MIPS CPUs in their systems either as a supporting controller or to replace an ARM or other CPU in their SoC. We’ve had several customers request the multi-architecture debug solution.”

Lauterbach will be hosting a free workshop at the 2016 UK Device Developers' Conference. Entitled “How to Optimise ARM Cortex-M Code and Build Better Embedded Systems”, this 2-hour presentation will explain all the Cortex-M debug Coresight bits and show how they can be used to debug and analyse an embedded system.