DSPI_FIFO – SPI master slave enhanced with detectors

The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, even from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows to select clock polarity and choose two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. – A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines – explains Jacek Hanke, CEO at Digital Core Design – so the data is simultaneously transmitted and received.

The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communication.

A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress.

A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.

The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.

DCD’s IP Core is technology independent and silicon proven design. It is fully customizable, which means it is delivered in the exact configuration of customer’s requirements. - There is no need to pay extra for not used features and wasted silicon – ends Hanke. The DSPI_FIFO includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Key features:

• SPI Master
• Master and Multi-master operations
• Two modes of operation: SPI mode and FIFO mode
• 8 SPI slave select lines
• System error detection
• Mode fault error
• Write collision error
• Interrupt generation
• Supports speeds up 1/4 of system clock
• Bit rates generated 1/4 - 1/512 of system clock.
• Four transfer formats supported
• Simple interface allows easy connection to microcontrollers
• SPI Slave
• Slave operation
• Two modes of operation: SPI mode and FIFO mode
• System error detection
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to microcontrollers
  • Four transfer formats supported
  • Fully synthesizable
  • Two DMA Modes allows single and multi-transfer
  • In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
  • Optional FIFO size extension to 128, 256 or 512 Bytes
  • Available system interface wrappers:
  • AMBA - APB Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Versatile interrupt system:
  • Single interrupt output with eight maskable interrupting conditions
  • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
  • Each FIFO can be programmed for four different interrupt levels
  • Watch dog timer for each receiver
  • Automatic wake-up mode for multidrop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receiver timeout mode