Docea announces power and thermal modeling and analysis capabilities for Aceplorer, previews AcePowerModeler to close loop between implementation and architectural modeling at 47th DAC

Two main challenges face system architects for power simulation at a high abstraction level:

1. How to describe the activity and capture a realistic scenario for the architecture and
2. Where to get power models to describe the architecture.

Aceplorer 2.0 answers the first challenge by linking to virtual platforms to allow the import of traces describing the activity in standard VCD (Value Change Dump) format. With new platforms and systems-on-chip embedding more and more functions and software, the complexity of use cases and use scenarios is exploding. With this link, architects can continue to optimize the performance of their designs on their current flow, and have the possibility to measure the impact of complex scenarios and embedded software on the power consumption of their design’s architecture. Since the VCD output format is a standard, Aceplorer can now be used in combination with any performance analysis flow.


As for the second challenge, Ghislain Kaiser, CEO, Docea Power, noted, “In most design projects, around 80% of the blocks are reused with some variation from previous designs. Within these legacy designs, there is a tremendous amount of data from power simulations at the gate level or from netlists and from measurements. It can take hours of simulations and testbench setups to extract this data, and now with Aceplorer 2.0 it can be exploited by system architects.”


AcePowerModeler automates the generation of power models from power figures and tables extracted from low level descriptions and from measurements. These models can be re-used by architects at a higher abstraction level for much faster simulations allowing architectural exploration and optimization with no loss of accuracy.