Digital tool suite achieves GLOBALFOUNDRIES 22FDX

Through the certification process, the Cadence tools have been confirmed to meet all of GF’s accuracy criteria for its Fully Depleted Silicon-On-Insulator (FD-SOI) architecture, and customers using the Cadence digital tool suite on the GF 22FDX process technology can optimise power, performance and area (PPA) and reduce time-to-market.

To facilitate the adoption of GF’s 22FDX process technology, the following Cadence tools that offer 22FDX body bias support are supported in the GF design flow:

• Innovus Implementation System: An advanced physical implementation tool, incorporating a massively parallel architecture that helps designers deliver high-quality SoCs in less time with PPA.
• Genus Synthesis Solution: An RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to five times faster synthesis turnaround times.
• Tempus Timing Signoff Solution: A complete timing analysis tool that improves signoff timing closure via massively parallel processing and physically aware timing optimisation.
• Voltus IC Power Integrity Solution: A cell-level power integrity solution that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip SoC power signoff accuracy.
• Voltus-Fi Custom Power Integrity Solution: A transistor-level power integrity solution that supports comprehensive EM/IR design rules and requirements while providing SPICE-level power signoff accuracy for analog, memory and custom digital IP blocks.
• Quantus Extraction Solution: A single, unified parasitic extraction tool that supports cell-level and transistor-level extractions during design implementation and signoff and provides high accuracy versus foundry golden.
• Physical Verification System: Includes advanced technologies and rule decks to support design rule checks (DRCs), layout versus schematic (LVS), advanced metal fill, voltage-dependent checks and in-design verification.
• Litho Physical Analyser: Signoff solution that enables designers to detect and automatically fix process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP.
• Litho Electrical Analyser: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions and the generation of fixing guidelines from partial layout to accelerate analog design convergence.

GF chose the Fusion F1 DSP to demonstrate the compelling PPA results with the 22FDX node, which is designed for low-cost, low-energy IoT sensing and connectivity applications. The Fusion F1 DSP provides the power-efficient control and signal processing demanded by emerging IoT applications like NB-IoT-based modems and other battery-powered products.

“Through our collaboration with Cadence, we’ve verified that the Cadence methodology meets our accuracy, frequency, power and cell utilisation requirements,” said Richard Trihy, Senior Director, Design Enablement at GF. “The certification of the Cadence digital tool suite allows our mutual customers to reach their PPA targets and to experience the benefits associated with the GF 22FDX body bias techniques that are key differentiators with our process technology.”

KT Moore, vice president, product management in the Digital & Signoff Group at Cadence, added: “Through the integration and innovation offered by our full-flow digital tool suite that was certified using the Tensilica Fusion F1 DSP, customers designing with the GF 22FDX process technology can converge on PPA targets faster. GF performed thorough correlation checks on the Cadence flow, thereby giving users added confidence that they can successfully implement robust designs quickly and stay ahead of the competition in their respective markets.”