Digital and signoff tools enabled on process technologies

The Cadence custom/analogue, digital and signoff tools meet Samsung’s requirements, which can enable foundry customers to create complex, advanced-node mobile and other vertical market designs using Samsung’s 7LPP and 8LPP process technologies. 

The digital and signoff tools currently enabled on the Samsung 7LPP process include the Innovus Implementation System and Physical Verification System for DRC. The custom/analogue tools enabled on the Samsung 7LPP process include the Virtuoso Advanced-Node Platform, which consists of the Spectre Accelerated Parallel Simulator (APS), the Spectre Extensive Partitioning Simulator (XPS), the Virtuoso ADE Product Suite, the Virtuoso Layout Suite, and the Virtuoso Schematic Editor. The Quantus QRC Extraction Solution and Physical Verification System for Layout Versus Schematic (LVS) and Manufacturability and Variability Solutions (MVS) are expected to be enabled on the 7nm LPP process by the end of June 2017.

The digital and signoff tools currently enabled on the Samsung 8LPP process include the Innovus Implementation System, Quantus QRC Extraction Solution and Physical Verification System. The custom/analogue tools enabled on the Samsung 8LPP process include the Virtuoso Advanced-Node Platform, which consists of the Spectre Accelerated Parallel Simulator (APS), Spectre Extensive Partitioning Simulator (XPS), the Virtuoso ADE Product Suite, the Virtuoso Layout Suite, and the Virtuoso Schematic Editor.

“We’ve worked closely with Cadence to ensure that its custom/analogue, digital and signoff tools enable customers to quickly and easily experience the benefits of our advanced-node process technologies,” said Jaehong Park, Senior Vice President of the Foundry Design Team at Samsung Electronics. “Enabling tools early is essential for our customers to deliver designs to their high-volume customers within tight market windows.”

“The Cadence tools that are enabled allow customers to achieve optimised power, performance and area results and remain competitive within their respective markets,” said Dr. Anirudh Devgan, Executive Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The close collaboration and efficient working model between Cadence and Samsung Foundry provides customers with confidence that these complex, advanced-node FinFET designs can be implemented quickly.”