Design tools enable 3D-ICs for use in next-gen CPUs

16th January 2015

ANSYS

Barney Scott

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ANSYS has announced that Fujitsu is using its power noise and reliability solutions to create 3D ICs to meet performance requirements for next-gen high-performance CPUs. These chips leverage 3D-IC architecture to gain power, performance and price advantages, but the configuration increases design complexity and the challenges associated with power and thermal management.

ANSYS’ RedHawk and Sentinel provide Fujitsu with the ability to perform voltage drop, electromigration and thermal reliability analysis of its large processor designs by delivering full-chip capacity, fast turnaround and accurate sign-off.

Finding the optimal floor plan for 3D-IC requires placement of TSV, as well as the power/ground network. This added complexity necessitates early-stage floor planning, analysis and debugging, as power and thermal issues become difficult to resolve later in the design process. Using RedHawk, Fujitsu can explore various TSV placement options to meet chips’ power noise and reliability requirements.

“The use of 3D-IC architecture adds complexity that needs to be addressed early in the design process,” said Tatsumi Nakada, Director, Next Generation LSI Packaging Development Office, Fujitsu. “By using RedHawk and Sentinel, we are able to optimise our design to meet power, performance and chip cost targets.”

“Industry-leading companies such as Fujitsu need to continuously push the envelope to meet their customers’ needs,” said Fares Mubarak, Vice President and General Manager, ANSYS. “ANSYS is committed to delivering best-in-class solutions that address our customers’ growing power noise and reliability challenges.”