Design tools complement 28nm Super Low Power process to achieve 2.0GHz performance

Cadence tools used in this design include Encounter Digital Implementation System, Encounter RTL Compiler, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Encounter Conformal Equivalence Checker, Physical Verification System and Litho Physical Analyzer. The flow incorporated physical IP technology from the ARM POP IPsuite to leverage the full performance range of the 28nm-SLP process.

Based on the success of this design, Cadence and GLOBALFOUNDRIES have also completed the tapeout of a second chip using the latest ARM Cortex-A17 processor RTL, achieving a 23% single-core area reduction versus the previous tapeout, while meeting the 2.0GHz maximum frequency signoff target. The second tapeout included the full suite of ARM POP IP, including the optimised memory instances for Cortex-A17. In addition, the Cadence Voltus IC Power Integrity solution was used throughout the design of the next-gen quad-core tapeout to guide and validate the power grid and enable the implementation of advanced power shutoff technologies. Encounter Conformal Low Power was used to verify the power-intent specification for the design.

“Silicon to simulation correlation at 2.0GHz performance further validates the maturity of our 28nm-SLP process, which continues to deliver silicon-proven performance and power targets our high-volume mid-range mobile customers demand,” said Gregg Bartlett, senior vice president, Product Management Group at GLOBALFOUNDRIES. “We collaborated closely with Cadence and ARM to deliver these designs using our 28nm-SLP process, and our customers can reap the benefits when using the ARM Cortex-A17 processor and the Cadence design flow.”

“SoCs based on the ARM Cortex-A17 processor deliver premium cost-optimised performance for multiple devices including mainstream mobile and other consumer products that take advantage of the millions of software applications designed for 32-bit ARM-based cores,” commented Dipesh Patel, Executive Vice President and General Manager, Physical Design Group, ARM. “The Cortex-A17 core is purpose-built for high performance within thermally restricted devices, and the partnership between ARM, Cadence and GLOBALFOUNDRIES enables designers to use it to meet an array of complex requirements. We also expect it to drive innovation in new applications such as high-end wearables.”

“The full Cadence suite with integrated signoff enabled GLOBALFOUNDRIES to deliver working silicon with high accuracy,” added Anirudh Devgan, Senior Vice President, Digital and Signoff Group, Cadence. “GLOBALFOUNDRIES can now offer an efficient process with an integrated Cadence flow that can allow designers to bring low-power, high-performance designs to the market within tight windows.”