Design tools achieve TSMC certification for 10nm FinFET

The Encounter Digital Implementation system has concluded 16nm FinFET Plus (16FF+) V1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE models. The system provides key technology for 16nm and 10nm process enablement and supports floorplanning, placement and routing with integrated colour-/pin-access-/variability-aware timing closure, clock tree and power optimisation. Cadence and TSMC are also working on the certification of Cadence’s recently introduced Innovus Implementation System, with 16FF+ V1.0 certification targeted to be completed by the end of April 2015 and 10nm certification targeted to be completed by June 2015.

The Tempus Timing Signoff solution is a colour-aware timing signoff and signal integrity analysis tool which supports 10nm design requirements for waveform propagation, Miller Effect, ultra-low power and variation associated with multi-patterning and FinFET technologies.

The Voltus IC Power Integrity solution, a cell-based, full-chip power signoff tool, supports 10nm design requirements including colour-aware layout patterning on power grid and electromigration (EM) rules. Together with other Cadence products, the power signoff solution is able to handle the needed accuracy requirements for the 10nm process in design analysis and optimisation, including IR-drop and EM, IC chip and package co-analysis.

The Voltus-Fi Custom Power Integrity solution is a SPICE-accurate, transistor-level power signoff tool which is used on analogue, memory and custom digital IP blocks. The solution supports 10nm EM/IR drop design requirements down to the device level, including ‘silicon-width’ EM rules.

The Quantus QRC Extraction solution, a single, unified tool, delivers a highly accurate, scalable solution that supports both cell-level and transistor-level extractions during design implementation and signoff. The solution provides required accuracy with quasi-3D FEOL/MEOL modelling, multi-patterning support, multi-colouring and 3D modelling using the Quantus Field Solver.

The Virtuoso Custom IC advanced-node platform is a custom design platform which offers comprehensive support for 10nm process requirements, including multi-patterning support, 10nm and colour-based OpenAccess constraints and highly matched place-and-route device arrays to account for density-gradient effects. The platform also offers support for user-assigned mask colours in schematic, cut metal, colour back-annotation flow using the Cadence Physical Verification system and 10nm support for Virtuoso Layout Suite for Electrically Aware Design.

The Spectre simulation platform, which is comprised of the Spectre Circuit Simulator, the Spectre Accelerated Parallel Simulator and the Spectre eXtensive Partitioning Simulator, delivers fast and accurate circuit simulation with full support of 10nm device models and parasitics.

The Physical Verification system, a full-chip system provides a multi-patterning decomposition and chip-finishing solution, integrates with the Virtuoso Custom IC platform and other Cadence tools to significantly reduce iterations and achieve faster design closure.

The Litho Electrical Analyzer integrates the TSMC 10nm Layout Dependent Effects (LDE) engine to deliver the 10nm TSMC-certified Virtuoso-LDE flow, which allows custom analogue designers to integrate LDE earlier in the design flow and accelerate analogue design convergence.

Furthermore, TSMC’s 10nm libraries are created using the Cadence Virtuoso Liberate Characterization solution and Spectre Circuit Simulator.

“We collaborated very closely with Cadence on the certification process so our mutual customers can enjoy the performance and power improvements available with advanced FinFET process technologies,” said Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC. “The certification of Cadence’s custom/analogue and digital implementation and signoff tools ensures design solution readiness for customers to achieve reduced iterations and improved predictability with 10nm FinFET designs.”

“Customers can begin leveraging 10nm FinFET solutions to overcome design complexity and get to market faster, and we are already seeing success with early customer design starts,” said Dr. Chi-Ping Hsu, Senior Vice President and CSO, EDA, Cadence. “TSMC and Cadence have had a long history of collaboration that has led to continued advancements in silicon technology, and we plan to work together with our customers to drive innovations based on the latest process technologies.”