Design software enables faster time-to-market for FPGA designs

11th August 2014

Siobhan O'Gorman

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The Libero SoC version 11.4 comprehensive design software used for the development of FPGA SoC products, has been updated by Microsemi. The Libero SoC v11.4 software improves the runtime of the company's SmartFusion2 SoC FPGAs and IGLOO2 FPGAs by up to 35%. With an improved SmartDesign graphical design canvas along with improved text editor, design reporting and constraints editor capabilities, the software offers greater design efficiency.

The software's SERDES wizards are also improved, offering clocking options which allow for increased flexibility in mixing serial data rates. Together, these improvements reduce design creation complexity for users, resulting in a faster time-to-market for SERDES-based FPGA designs.

Full design flow support for the Linux open source operating system is also offered by the Libero SoC v11.4 software. The FlashPro Express tool that comes bundled with the software enables device programming and debugging capabilities for the Linux operating system. In turn, this allows users to stay in the same development environment throughout the entire design flow.

“Our overarching goal with the release of Libero SoC v11.4 design software is to create enhanced ease-of-use and design efficiency with improvements in various design wizards, editors and scripting engines, as well as vastly improved run times. These significant improvements help our customers get their FPGA-based solutions to market faster,” said Shakeel Peera, Senior Director of Product Line Marketing, Microsemi. “We also want to leverage the large and ever increasing corporate Linux operating system installed base and give our customers the ability to run an entire design exclusively through a comprehensive Linux design flow.”