Computer Simulation Technology (CST) announces closer cooperation and webcast with Cadence Design Systems, Inc.

As multiband devices shrink and frequencies increase, layout of packages, system in packages (SiP) and PCBs is becoming increasingly critical to maintain good signal and power integrity and to meet radiated emission requirements. Rule checkers can help to some extent, but electromagnetic field simulators are required to see the full picture, both in pre layout analysis and post-layout verification. Most layout tools have 2D simulators available that can offer good insights, but for high accuracy and to address layouts with non-planar elements such as wirebonds, a full 3D simulator is mandatory.

CST has offered a plug-in to Cadence tools for some years and more recently a direct import has become available that offers component recognition, layer editing and net and area selection. A major collaborative project now enables Cadence layout engineers to stay within their familiar environment while performing a full wave 3D extraction and EM analysis in the background. Results are back annotated to the Cadence environment. This EDA centric viewpoint vastly simplifies the workflow required to achieve design goals.

Simplifying the workflow for layout design and analysis will bring big benefits to the engineer working to get his designs accepted, stated Martin Timm, Director of Marketing, CST. Not having to learn a new environment or pass the design on to another department will save time and increase overall throughput significantly.

With increasing numbers of complex, multi-die packages being designed that run at GHz frequencies, package designers now require 3D full wave extraction of IC package structures, commented Brad Griffin, Product Management Director, SiP and IC Packaging, Cadence Design Systems. The seamless integration of CST's proven 3D full wave extraction engine with the Cadence SiP Signal and Power Integrity solution, unites two recognized leaders into a simplified IC package design flow.