Compiler drastically reduces design time for complex transport system
In order to deliver a complex 100G transport system design, Kansai-Chubu Net-Tech (KCN) utilised Cadence Design Systems' C-to-Silicon Compiler to shorten turnaround time by 40% compared to its traditional RTL process.
KCN used the SystemC-based design approach for the transport system pipelines, reducing code size by more than half, and used the C-to-Silicon Compiler high-level synthesis for quick iterations to tune the functional specification and generate the optimised RTL implementation.
By changing the design constraints to the C-to-Silicon Compiler, KCN was able to explore different micro-architectures and significantly reduced the place-and-route turnaround time. Fixing a place-and-route issue with traditional RTL design at Fujitsu took three days, but only half a day with the C-to-Silicon Compiler.
“Our highly integrated 100Gb/s transport systems operate at very high frequency, which presented a major design challenge,” said Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Kansai-Chubu Net-Tech. “By designing at a higher level of abstraction in SystemC, our design team was able to implement the customised hardware much more quickly and effectively."
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