Collaboration on SiFive’s RISC-V Core IP portfolio

As hardware design and development progresses based on this functional outline, the simulation model is the foundation that supports virtual prototypes for early software development well before silicon devices are available. These models also work with most industry-standard software IDEs and debuggers, and are available today from Imperas and approved Imperas EDA distribution partners.

The key requirements for processor simulation models are accuracy, performance, and usability. The Imperas models for SiFive processor IP are an Instruction Accurate (IA) programmer’s view representation of the full functionality of the core IP, including user, privileged, system, and debug modes, plus the configuration options for the RISC-V vector extensions and custom instructions.

The Imperas models deliver simulation performance of 100s to 1,000s of MIPS on a modestly configured host PC; as an example, the virtual platform model of the SiFive Freedom U540 SoC with five SiFive CPU cores boots SMP Linux in under ten seconds.

The full usability of the Imperas models is coupled with the Imperas debug and analysis tools that support multicore design tasks, including OS porting and abstractions for application development. In addition, the Imperas simulator with proprietary code-morphing simulation technology can be integrated within other standard EDA environments such as SystemC, SystemVerilog, and well-known simulation/emulation tools from Cadence, Siemens EDA, and Synopsys plus the cloud-based offering from Metrics Technologies.

In the era of multicore design, the importance of software debug and analysis has never been greater. The Imperas tools enable developers to introspect the activities across the full multicore SoC, including interactions across the design hierarchy for core-to-core and core-to-peripherals, with access and control using the software under development without modification. Increasingly, software functionality is part of the end system certifications in high-reliability applications such as Automotive, Mil-Aero, Medical, Industrial IoT, and other safety-critical systems.

“The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development,” said Chris Jones, VP product marketing, SiFive. “The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.”

“SoC projects are all about partnerships; hardware and software engineers working together, with a complete ecosystem of supporters,” added Phil Dworsky, Director, Strategic Alliances, SiFive. “With this Imperas collaboration, our mutual customers will benefit from the availability of SiFive qualified models that are compatible with the mainstream EDA tool flows.”

“The SiFive Core IP portfolio covers the spectrum of the RISC-V ISA, from embedded controllers, to multiprocessors supporting SMP Linux, plus the latest vector-based accelerators,” said Simon Davidmann, CEO, Imperas Software. “These are the starting points for the next generation of domain-specific devices across almost all market segments and applications. Imperas is ready to support designs featuring single-core through to many-core arrays with our SiFive qualified models.”