Design
Cavium’s New OCTEON III family of processors feature latest Imagination Technologies MIPSr5 architecture
Imagination Technologies today announced that long-time MIPS licensee Cavium has licensed and incorporated the latest Release 5 MIPS architecture (MIPSr5) features, including hardware virtualization, in all members of its ultra-high-performance 1 – 48 core OCTEON III family of products.
Jim M. Raghib Hussain, corporate VP/GM and CTO, Cavium, says: “The MIPSr5 architecture enhancements from Imagination combined with Cavium’s in-house design expertise will help create the most advanced MIPS 64-bit processor in the industry and will serve to further extend our leadership in the network infrastructure market.”
For more than 20 years, the 64-bit MIPS64 architecture has powered some of the industry’s most innovative networking and communications products, supported by a broad and mature infrastructure and ecosystem. The MIPS64 architecture is already at the heart of a wide range of Cavium’s OCTEON processors, and now will also power Cavium’s OCTEON III family of 1 – 48 core processors that deliver over 100Gbps of application performance per chip, and provide among the highest compute power of any standards-based communications processor chip with 120GHz of 64-bit compute processing per chip.
About MIPS processors
Imagination’s family of MIPS processors are ideal for products where ultra low-power, compact silicon area and a high level of integration are required. MIPS processor IP cores and architectures range from ultra-low power 32-bit microcontrollers to scalable 32-bit and 64-bit multi-core solutions for advanced application and network processing platforms.
Based on a heritage built and continuously innovated over more than three decades, Imagination’s MIPS architecture is the industry’s most efficient RISC architecture, delivering the best performance and lowest power consumption in a given silicon area. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage in the same power, thermal and area budget.
The seamlessly compatible MIPS32 and MIPS64 instruction-set architectures (ISAs) allow customers to port from one generation to the next while fully preserving their investment in existing software. MIPSr5 architecture incorporates important functionality including hardware virtualization and SIMD (Single Instruction Multiple Data) modules.