Cadence Announces Comprehensive SOI Design Hub

Cadence has been working with IBM, the leading SOI foundry, and with ARM to deliver methodologies, reference flows, IP access and services for SOI design. This includes the recent delivery of a 45-nanometer SOI SerDes receiver. Cadence also recently announced a joint development agreement with IBM to develop complex IP, including SOI designs, as part of the Cadence open integration platform. Forty-five-nanometer SOI technology offers up to 30 percent performance improvement or 40 percent power reduction when compared to the industry-standard bulk CMOS technology.

The Cadence open integration platform is a key component of the EDA360 vision, which, among other things, helps integrators close the profitability gap by providing new capabilities for IP creation, selection and integration.

“Cadence and IBM have collaborated for several SOI process generations to deliver silicon-proven methodology to our mutual customers,” said Mark Ireland, vice president, Semiconductor Products and Services, IBM. “Providing this proven technology and Cadence services expertise is an excellent way to help customers in adopting SOI technology.”

Through the SOI Design Hub, Cadence now offers three new solutions: An SOI IP porting service, where Cadence Services migrates analog, digital, and mixed-signal IP blocks to an SOI process technology, and delivers a self-contained macro that will integrate smoothly with the target design environment; turnkey design services, where customers can outsource any aspect of their design to the SOI design-experienced Cadence team; and a software-as-a-service (SaaS) offering with a complete do-it-yourself IP porting environment that provides access to a production-proven Cadence design environment within a secure IT infrastructure.

“As adoption of SOI technology continues to grow it is important to have a central point for accessing design enablement tools and IP to accelerate the design cycle and industry adoption,” said John Heinlein, vice president of marketing, ARM, Physical IP division. “The Cadence SOI Design Hub, coupled with ARM physical and processor IP, provides engineers a silicon-proven route for leveraging this advanced technology to deliver high-performance, low-power consumer devices while reducing design risk and cost.”

“We’ve been working diligently with IBM and ARM to make SOI adoption easier for our customers and enable them to benefit from this advanced technology,” said Vishal Kapoor, vice president of product management at Cadence. “The new SOI Design Hub will help realize designs for those interested in leveraging the power and performance benefits of this technology with the solutions and services they need to ensure success.”

“This innovative offering by Cadence provides a range of new options for companies to leverage the power efficiency and integration benefits of SOI technology in their products,” said Horacio Mendez, executive director of the SOI Industry Consortium. “The SOI Design Hub is a significant addition to the SOI design chain for the electronics industry.”