Cadence, GloFo collaborate on 12LP/12LP+ Solutions

The collaboration also supports chiplet-based PHY IP and Cadence’s flagship 16G multi-protocol SerDes.

The first product on the GF 12LP platform is the Cadence 16G Multi-Link and Multi-Protocol PHY, which is based on a high-performance multi-protocol architecture already well-proven in high volume production.

“GF is working closely with Cadence to enable high-performance SerDes and advanced memory interfaces to support our mutual customers building advanced SoCs for high-performance computing, aerospace and defense applications, cloud/data centre servers, AI accelerators, and wired and wireless networking applications, as well as designers and customers leveraging die-to-die connectivity and pursuing chiplet architectures,” said Mark Ireland, vice president of ecosystem and design solutions at GF. “The combination of our 12LP platform, specialised 12LP+ FinFET solution offerings, and Cadence design IP enables our mutual customers to win in their respective markets through fast and efficient development and certification of their complex SoCs with compelling performance, power, and area results.”

“Cadence is making significant investments in enabling advanced IP. Together with GF, we are delivering mature, silicon-proven high-performance IP solutions that meet the needs of market-leading industrial and aerospace and defense companies,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Our expanding IP portfolio on the GF 12LP/LP+ process node unlocks a new set of customers for Cadence, allowing us to help accelerate development and time to market for their next-generation SoCs.”

GF’s most advanced FinFET solution, 12LP+ builds upon GF’s established 14nm/12LP platform, of which GF has shipped more than one million wafers.

By partnering closely and learning from AI customers, GF developed 12LP+ to provide greater differentiation and increased value for designers in the AI space while further minimising their development and production costs.

Cadence’s broad design IP portfolio also supports the company’s Intelligent System Design strategy.

The Cadence flagship 16G multi-protocol PHY supporting PCI Express (PCIe) 4.0 and 10G-KR on the GF 12LP process is available now. 

Advanced memory IP supporting the DDR4, DDR5, LPDDR4X, LPDDR5 and GDDR6 protocols, as well as chiplet-based PHY IP and high-performance SerDes IP for GF’s 12LP+ solution is in development, and design kits are expected to be available in 1H of 2021.