ARM Cycle Models enable cache coherent interconnect IP

Arteris has been a long-time partner with the Cycle Model team at ARM, with many mutual customers and licensed ARM processor Cycle Models, Performance Analysis Kits and SoC Designer Plus for its own development use in 2014. The ARM Cycle Models provide fast, 100% cycle accurate simulation of the latest ARM processor IP, enabling the Arteris team to create a highly scalable infrastructure to verify compliance with the ARM AMBA ACE protocol and to optimise the Ncore interconnect IP for a broad range of system-level use cases. The SoC Designer Plus Swap & Play technology was instrumental in the creation of fast virtual platforms running software test suites to characterise system bandwidth and latency for a multitude of use cases.

Javier Orensanz, General Manager, Development Solutions Group, ARM, commented: “ARM Cycle Models provide early, secure access to ARM’s leading edge IP. Enabling Arteris to integrate this technology into their development infrastructure highlights ARM’s commitment to enabling design optimisation, time-to-market and cost-efficiency gains for our ecosystem partners.”

K. Charles Janac, President and CEO, Arteris, commented: “ARM’s system-level modelling and virtual prototyping technologies have been critical to development of our new Ncore cache coherent technology. Being able to quickly integrate the latest ARM IP into our testing infrastructure and simulate it on a large scale has helped us increase the quality of our product and produce a world-class performance optimisation and verification environment.”