Design

Lattice Semiconductor has announced the immediate availability of Version 1.3 of its ispLEVER Classic design tool suite. Version 1.3 includes updated support for Lattice CPLDs (Complex Programmable Logic Devices), including the widely popular ispMACH 4000 device family. Designers can quickly download, for free, ispLEVER Classic for Windows, as well as optional Synopsys Synplify logic synthesis and Aldec Active-HDL simulator modules from: www.latt...

EDA Solutions has announced the availability of version 14.10 of Tanner EDA’s Tanner Tools Pro and HiPer Silicon design software, including a new interactive autorouter, SDL Router, and a layout device generator, DevGen. Both these additions increase designers’ productivity and speed up development of full custom analogue IC and MEMS design.

Altium continues to provide new features in Altium Designer, its electronics design software, to help electronics designers stay continuously updated on new technology and trends. “We think the days of an industry model that somehow forces users to wait for significant new releases and features, that appear only once every few years, are numbered,” says Nick Martin, CEO of Altium.

Concept Engineering today announced that Oasys Design Systems, Inc., developer of the RealTime Designer full-chip physical register transfer-level (RTL) synthesis product, has signed a worldwide OEM license for Concept Engineering′s Nlview visualization engine. Nlview is integrated into RealTime Designer to power its debugging GUI. Design engineers using RealTime Designer bundled with Nlview benefit from a high-performance, high-capacity de...

ARM today announced at DAC, San Francisco, Calif., that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM Fast Models Enablement Program. Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers. This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of the...

EDA Solutions has announced the availability of version 14.0 of Tanner EDA’s Tanner Tools Pro and HiPer Silicon design software, including a new interactive autorouter, SDL Router, and a layout device generator, DevGen. Both these additions increase designers’ productivity and speed up development of full custom analogue IC and MEMS design.

Real Intent is showcasing and demonstrating new software products and capabilities of its Ascent, Meridian and PureTime verification families at the Design Automation Conference (DAC09). Ascent now includes the first commercially available automated solution to ensure X-robust designs, available through its Path-Based Verification (PBV) product.

Synopsys has introduced Galaxy Constraint Analyzer, a new tool which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints. Correctness and consistency lead to more efficient runtimes in Synopsys’ Design Compiler synthe...

Fairchild Semiconductor provides designers of portable applications a web-based simulation tool to quickly and accurately assess the performance of advanced load switches in actual application circuits. The IntelliMAX design tool is unlike other simulation tools because it offers an intuitive, user-friendly environment containing models of Fairchild’s advanced load switches in pre-defined application circuits. This feature enables designers to...

STMicroelectronics will participate as presenter or co-author of several papers at the DAC 2009 (Design Automation Conference), which takes place from July 26-31, 2009, in San Francisco, California. ST’s contributions to the conference cover advances in design methodologies and automation in the areas of 3-D stacking for complex SoC (System-on-Chip) ICs, physical- and system-level chip design, and IC reliability.