Design
Cadence Debuts Verification Computing Platform, Accelerating Time and Improving Quality of System Development
Cadence Design Systems announced the first fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better quality em...
Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips
Cadence Design Systems announced that it has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal e...
Synaptics Gesture Suite Now Available For Popular Linux Operating Systems
Synaptics Inc. (NASDAQ: SYNA), a leading developer of human interface solutions for mobile computing, communications, and entertainment devices, today announced the extension of its industry-leading Synaptics Gesture Suite™ to the Linux operating system environment. This release extends the Synaptics Gesture Suite—which includes sophisticated multi-finger gestures—to OEMs that offer Linux-based solutions.
TI's new FilterPro v3.0 design tool eases amplifier filter design
Texas Instruments introduced the latest version of its popular FilterPro design tool. FilterPro v3.0 offers a new and improved user interface and a more accurate and robust filter design engine, thanks to updates, such as ability to adjust passive element tolerances and view response variations; scale passive component values; and view and export filter performance data to Excel.
Green Hills Software INTEGRITY RTOS available on all Extreme Engineering Solutions, Inc. (X-ES) boards with Intel® Core™ i7 processors
Green Hills Software and Extreme Engineering Solutions, Inc announced the availability of INTEGRITY RTOS board support packages (BSPs) on all Extreme Engineering Solutions embedded computing products based on the new Intel Core i7 processor.
Teridian Semiconductor Corporation Approves Datatronics Modem Transformer For Reference Designs
Teridian Semiconductor Corporation has approved the new Model PT79281 V.22bis Modem Transformer from Datatronic Distribution, Inc., for use with its reference designs that include the Teridian IC Models 73M1903, 73M1903C, 73M2901CE and 73M2901CL.
Magma Announces SiliconSmart ACE Memory Characterization – Embedded FineSim Pro Enables Most Accurate Characterization of Timing, Power and Noise Models
Magma Design Automation announced SiliconSmart ACE Memory Characterization, the latest addition to the industry-standard SiliconSmart IP characterization and modeling product line. By embedding Magma’s ultra-fast FineSim Pro simulator and leveraging Magma’s proprietary optimization technology for memory circuits, SiliconSmart ACE Memory Characterization provides faster, more accurate timing, power and noise characterization of memory instanc...
Magma’s Titan Supports IPL 1.0 Standard for Interoperable Process Design Kits
Magma Design Automation announced today that the Titan Mixed-Signal Platform has been validated to support the interoperability and accuracy requirements of the IPL 1.0 Interoperable Process Design Kit (iPDK) standard. The Interoperable PDK Libraries (IPL) Alliance standard eliminates the need to develop multiple proprietary PDKs and design databases, reducing development costs, shortening delivery schedules and providing designers earlier acces...
Altium - Learn to eliminate risk and get designs right, first time
Learn how to eliminate the fear and uncertainty of releasing an electronics design to production at Altium's webinars 'Right First Time: Design Configuration and Release Process Management'. The first English webinar will take place on May 19, 2010 at 2 pm CEST,12 pm GMT (at 10 am CEST in German, at 1pm CEST in French).
VarioTAP supports non JTAG Interfaces
During its „Boundary Scan Days Germany“, GOEPEL electronic introduced the further development of the innovative emulation technology VarioTAP for the support of non JTAG debug interfaces. The new features enable the broad coverage of various proprietary debug architectures of different chip manufacturers without utilising processor specific pods. The first interfaces to be supported are the so called BDM interface (Background Debug Mode) and...