28mn design taped out using timing signoff tool

Enabling customers to shrink timing signoff closure and analysis turnaround time to a minimum, the Tempus solution is the lead tool in a new class of parallel timing signoff tools and capabilities. Designs are produced with less pessimism, area and power consumption through physically aware and path-based analysis optimisation. By combining the massively parallelized capabilities of Tempus and QRC together and leveraging native database formats, Hitachi was able to improve time-to-tapeout well beyond those of existing mixed tool flows.

“We have worked very closely with Hitachi to ensure that the Tempus solution fulfills the requirements of its next generation of product design cycles,” said Anirudh Devgan, senior vice president of the Digital and Signoff Group (DSG) at Cadence. “The Tempus solution is the first innovation in a platform of signoff tools that brings a scalable and complete signoff solution to our customers now and at smaller process nodes.”