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Release of Spartan-6 PCI Express Grabber Board supporting CameraLink PoCL

7th September 2010

ES Admin

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Tokyo Electron Device Limited has today announced the release of the TB-6S-LX150T-GB-R half-size PCI Express frame-grabber board which features a Spartan(R)-6 FPGA from Xilinx and supports the CameraLink PoCL (Power over Camera Link) interface standard.

Released under TED's inrevium brand, the TB-6S-LX150T-GB-R incorporates a high-performance Spartan-6 LX150T FPGA with an internal 3.125 Gbps (max.) transceiver in Xilinx Spartan-6 low-power FPGAs family. By supporting the CameraLink PoCL standard, the board facilitates the design of more compact products by allowing the connection of PoCL-capable cameras via a single cable and providing power supply and control as well as supporting the wide-band data transmission and image processing required for video data. This makes the board ideal for Machine Vision applications that require high- speed image transmission and image processing, such as imaging and inspection systems in industrial or medical equipment.

The board can capture images simultaneously from two PoCL-Base channels and one PoCL-Lite channel via 4-lane PCI Express Gen1 and includes 512 Mbyte of on-board image buffer memory. The availability of FPGA designs and a PC application also help significantly shorten customer product development times.

Also available is the TB-6S-GB-SHR which is based on the TB-6S-LX150T-GB-R and supports ultra-high-resolution cameras with pixel shift technology from CIS Corporation. Because this product uses the FPGA for hardware-based execution of operations commonly required by PC applications, such as pixel data sorting and Bayer conversion, it can shorten the image capture latency and reduce the processing load on the PC so that image data can transfer at faster speeds and with higher quality.

TED also offers volume production and custom modifications based on this product.

Key TB-6S-LX150T-GB-R Specifications

・FPGA: XC6SLX150T-3FGG676C

・Memory: DDR2 SDRAM chip x 2

・Interfaces

- PoCL-Lite x 1ch

- PoCL-Base x 2ch

- UART

- RS-422

- GPIO

・PCI Express Gen 1 x 4 lanes

・General-purpose pin header

・FPGA design and PC application included

- FPGA configuration data

- FPGA design source code (excludes PCI Express and DMA IP core)

- Image capture PC application