SRAM enables real-time image processing for driverless cars

When testing the SRAM in a state-of-the-art 16nm process, it achieved both 688ps high-speed operation under the low-voltage condition of 0.7V and the industry-leading high level integration density of 3.6Mb/mm².

Recently, in-vehicle infotainment systems, such as car navigation systems and ADASs, have achieved dramatic progress in preparation for the autonomous cars of the future. In these systems, real-time image processing technologies are critical for realising autonomous-driving vehicles, and there are limits to improve this real-time processing capability by only increasing the integration density with even finer feature sizes and using higher clock frequencies.

Due to increasing variations in device elements associated with finer feature sizes in semiconductor processes, there has been a trend for device lower limit operating voltages to become worse. To resolve this issue, circuit technology ("assist circuits") that uses circuit improvements was introduced. Previously, an optimisation in which the word line voltage was lowered slightly at access time to ensure stable operation during read operations.

This technique, however, had issues such as the operating margin during write being degraded and the read speed being reduced significantly. Renesas proposed, and then adopted, the assist circuit method for single-ported SRAM, which takes advantage of the FinFET device characteristics and, inversely compared to the early method, slightly increases the word line voltage and adjusts the pulse widths used during read and write operations. Then, Renesas has extended this assist circuit technology developed for single-ported SRAM and adopted it in the dual-ported SRAM for image processing.

Unlike single-ported SRAM, for dual-ported SRAM there are several different layout topologies for the bit cell. Although a planar MOSFET structure had been adopted up to now in processes through the 28nm generation, Renesas has adopted a new FinFET device, which adopts a fin structure that suppresses process variations in the 16nm process and clearly improves device characteristics. This new FinFET device has extremely strict layout restrictions and it is difficult to use the layout structure that was optimal for earlier planar type devices. Also, a symmetrical layout structure is required to operate the devices stably, since MOS characteristics fluctuate wildly. In this SRAM, Renesas has newly adopted a dual port memory cell optimised for this FinFET device to have superlative symmetry and has optimised the design of the peripheral circuits as SRAM for real-time image processing.

Renesas' newly-developed dual-ported SRAM for real-time image processing achieves both the speed and stable operation that were expected to be problematic as semiconductor fabrication processes move to even finer feature sizes, and furthermore suppresses power consumption and achieves reduced chip areas. The SRAM is expected to contribute significantly to improved real-time image processing performance in self-driving and leading-edge driver assistance systems of the future.

The SRAM will be adopted in Renesas' state-of-the-art SoCs in the 16nm FinFET process. By providing these devices with extraordinary speed, Renesas aims to contribute to the creation of a safe, secure and pleasant driving experience.