Soft core of programmable interrupt controller

4th November 2013

Nat Bowers

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Datasheet

DCD have today introduced the D8259, a soft core of programmable interrupt controller. Fully compatible with the 82C59A device, DCD’s IP core can manage up to 8-vectored priority interrupts for the processor. The D8259 can also be programmed to cascade and gain up to 64 vectored interrupts. Programming the D8259 to the Poll Command Mode, users can get more than 64 vectored interrupts.

The D8259 Package includes a fully automated testbench.It is easy to validate the whole package at each stage of SoC design flow, due to a complete set of tests. As with all other IP cores from Digital Core Design, the D8259 has a technology independent design, that can be implemented in a variety of process technologies.

Fully compatible with the 82C59A, the D8259 can operate in all 82C59A modes. It also supports all 82C59A features including: MCS80/85 and 8088/8086 processor modes, fully nested mode and special fully nested mode, special mask mode, buffered mode, pool command mode, cascade mode with master or slave selection, automatic end of interrupt mode, specific and non specific end of interrupt commands, automatic and specific rotation, edge and level triggered interrupt input modes, reading of interrupt request register and in service register through data bus, and writing and reading of interrupt mask register through data bus.

Key features of the D8259 include: 8 vectored priority interrupts, up to sixty-four vectored priority interrupts with cascading, fully synthesizable HDL Source Code, and static design and no internal tri-states.