Release of the next-gen SoC specification

With more than 200 million RapidIO fabric ports deployed worldwide at speeds of 6xN and 10xN 10-50 Gbps in analytics, wireless infrastructure, industrial and military applications, the 25xN 100 Gbps RapidIO Specification provides a proven, open standard interconnect fabric for systems requiring heterogeneous coherent scale out and non-volatile storage.

“With the public release of the 25xN 100 Gbps RapidIO Specification, our focus within our RapidIO Technical Working Group now shifts toward our Coherent Scale Out Task Group and our Non-Volatile Storage Task Group,” said Rick O’Connor, Executive Director of RapidIO. “Work on the Coherent Scale Out and Non-Volatile Storage draft specifications is progressing and we invite members of industry to join us and participate in defining these key building blocks for flexible, heterogeneous, coherent scale out of performance critical, low-latency applications over RapidIO fabrics.”

“The public release of the 25xN 100 Gbps RapidIO Specification is the culmination of efforts and contributions of RapidIO member companies,” said Paul Carson, Chairman of RapidIO and Director of IP Development at Texas Instruments. “This work extends the performance roadmap of RapidIO fabrics for use in heterogeneous systems for many years to come”.

“Open standard interconnects are key to ongoing energy efficiency and performance improvements across the entire SoC,” said Phil Bourekas, director of segment marketing, ARM. “The public availability of the 25xN 100 Gbps RapidIO Specification addresses ARM ecosystem developer requirements for coherent network infrastructure SoCs based on the ARMv8-A architecture, providing an available standard for systems at 5G and beyond.”

“IDT has a strategic commitment to RapidIO that spans over a decade and the public release of the 25xN 100 Gbps RapidIO Specification is a key enabling platform for wireless, HPC, cloud and industrial systems our customers are building”, said Ron Jew, General Manager, Wireless Infrastructure Products at IDT. “Through key R&D collaborations with global technology experts, such as CERN openlab, we’re able to ensure that our heterogeneous coherent scale out and storage over 100 Gbps RapidIO fabrics delivers the performance our customers in 5G infrastructure and advanced data analytics are looking for.”

“With the emergence of heterogeneous systems and next-gen non-volatile storage technologies beyond NAND Flash such as Resistive RAM (ReRAM), coherent fabric clusters will be key to driving scalable performance,” said Dr. Zvonimir Z. Bandić,

Director of Next Generation Platform Technologies at Western Digital Corporation. “We see the public release of the 25xN 100 Gbps RapidIO Specification as a key enabling building block for these coherent, non-volatile storage based systems.”

“Heterogeneous computing is becoming increasingly prevalent for our customers’ next-gen systems and our MIPS processor technology plays a key role in these systems,” said Jim Nicholas, EVP MIPS Processor IP at Imagination Technologies. “The release of the industry open standard 25xN 100 Gbps RapidIO Specification is a welcome addition to our ecosystem and we’ll look forward to future developments from the Coherent Scale Out Task Group.”

“With the end of Moore’s Law, coherent heterogeneous clusters with purpose-built accelerators will play a key role in driving performance of next-gen systems,” said Krste Asanović, Chairman of the RISC-V Foundation and Professor at UC Berkeley.“The public release of the 25xN 100 Gbps RapidIO Specification provides an excellent open platform for coherent clustering of RISC-V ISA-based processors.”

To learn more about the 25xN 100 Gbps RapidIO Specification and the demonstrations that will be showcased at the 2016 ISC High Performance Conference, please visit: RapidIO interconnect architecture specifications and RapidIO demonstrations at ISC.