Processors provide 75% better local memory area

15th January 2015

Siobhan O'Gorman

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Cadence Design Systems has announced the release of the Xtensa LX6 and the Xtensa 11, its 11th gen Tensilica Xtensa processors. The company’s latest gen processors allow users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency.

Very long word Instructions from 4 to 16B are enabled by enhancements in flexible length instruction extensions. This results in code size savings of up 25% compared to previous Xtensa generations, which in turn reduces local memory and cache size by up to 25%.

The 11th gen Tensilica Xtensa processors are also offered with an option for run-time power-down of portions of cache memories, which provides up to 75% local memory power savings in select operating scenarios with dynamic cache-way control.

Due to more efficient data cache block prefetch, functions such as MemCpy are now 6.5 times faster and the total number of system bus read operations are reduced by 23%. This lowers system power while boosting system performance. The dynamic switching power of the processor logic gates has also been reduced by 25%.

“These latest improvements put the Tensilica processors even further ahead of all other processor cores on the market that claim to offer configurability,” said Jack Guedj, Corporate Vice President, Tensilica products, Cadence. “Only Cadence automates the creation of both hardware and software development tools, allowing customers to create fully optimised processors for many applications in record time and with state-of-the-art software development tools.”