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PMC-Sierra Enables Wireless Backhaul Transport of Gigabit Ethernet Services over OTN

14th May 2010

PMC-Sierra

ES Admin

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PMC-Sierra the premier Internet infrastructure semiconductor solution provider, today introduced a complete reference design for its HyPHY chipset that supports standards-based transport of Ethernet-based services over the Optical Transport Network (OTN). ITU-T G.709 version 3 (10/2009) specifies direct mapping of Gigabit Ethernet (GE) to the OTN layer by defining a new container for the smallest Optical Data Unit (ODU), ODU0 (1.238 Gbit/s), ensuring complete timing transparency and bandwidth efficiency of Ethernet-based client signals. In conjunction with HyPHY's innovative support for timing synchronization over packet services, the reference design enables cost-optimized Layer 1 OTN networks with full support for Ethernet network timing distribution, a critical requirement for wireless backhaul applications.

PMC-Sierra's HyPHY chipset integrates support for mapping and multiplexing of GEs into sub-ODU1 (2.488Gbit/s) containers. The new PM5423-KIT ODU0 reference designleverages HyPHY's flexible packet interfaces and unique OTN Payload Tributary Mapping (OPTM) technology to add support for the newly defined OTN mapping modes, including:

* Transparent GE mapping and de-mapping into/from ODU0 via GMP; and
* ITU-T ODU0 multiplexing and de-multiplexing into/from higher order ODUks.

The exponential growth in Ethernet-based wireless backhaul, driven by 3G and LTE deployments, is accelerating the need for an efficient mechanism for GE transport over OTN, said Travis Karr, vice president and general manager of PMC-Sierra's Communication Products Division. This reference design enhances our HyPHY product family for multi-service convergence over OTN and provides a time-to-market advantage for our customers.

PMC-Sierra's ODU0 reference design can be used with either the PM5420 HyPHY 20G or PM5426 HyPHY 10G device. It includes a complete collateral suite, including a hardware reference design for evaluation, design specification documentation, and FPGA source RTL for integration.