Arasan Chip Systems Announces the Most Complete ONFI 3.1 NAND Controller IP & PHY Solution

To meet the ever increasing demand of faster data transfer rates in mobile storage applications, the ONFI 3.1 specification calls out performance of 400 MT/s using an NV-DDR2 interface and a 200 Mhz Clock. ONFI 3.1 improves on version ONFI 3.0 with more robust power sequencing to protect NAND flash, more flexible timing to support NAND usage in different topologies, improved parameters for testing, and other enhancements.

Focusing on high performance and high reliability, Arasan’s ONFI 3.1 NAND Flash Controller IP provides a high performance digital controller IP core with soft PHY and the hardened ONFI 3.1 compatible I/O pads supporting 1.8v and 3.3v operation. Compliant to the ONFI 3.1 electrical interface, Arasan’s IP core solution, delivered in RTL including synthesizable DLL and PLL, supports NV-DDR2 up to the specification’s full 400MT/s. The ONFI 3.1 compatible I/O pads support 200 Mhz NV-DDR2 operation at 1.8v. These pads differ from typical high speed DDR I/O pads in that they also support 3.3v I/O operation to enable backward compatibility with ONFI 2.x. The combined Controller IP with soft PHY and the I/O pads accelerates time-to-market by reducing SoC designers’ development time otherwise spent on ensuring high speed signal integrity.

Optionally, Arasan also provides a hardened ONFI 3.1 PHY delivered in GDSII including DLL and PLL. It includes the I/O pads compatible to ONFI 3.1 high speed operation at 1.8v or 3.3v. To support DDR running at 200 Mhz to achieve 400 MT/s, or 2.5ns window for sampling data, the DLL and PLL become the critical elements to accurately control the sampling clock and the control signals to avoid possible timing variations resulting from extreme temperature, supply voltage, and manufacturing process variations. Many memory subsystem digital designers have experienced tremendous challenges with ever increasing data transfer rates and differential signaling that requires very high signal integrity and low noise ratio; a problem which is usually dealt with by dedicated and experienced analog circuit designers. By using Arasan’s hardened ONFI 3.1 PHY solution with its proven DLL and PLL, SoC designers can now confidently and easily integrate the ONFI 3.1 PHY into their SoC using Arasan’s proven solution.

Arasan’s ONFI 3.1 NAND controller IP supports SLC, MLC, and TLC NAND Flash up to 128Gb, synchronous and asynchronous NAND interfaces, page size up to 16KB, BCH ECC engine correcting 32-bit or more errors, and eight chip-selects. When integrated in a SoC, Arasan’s ONFI 3.1 NAND Flash Controller IP also supports a variety of host bus interfaces for easy adoption into any system architecture with AMBA3-AXI/AHB/APB, OCP, or other custom buses. Arasan also provides ONFI 3.1 software stack and driver for system to facilitate and reduce the product development time.

Availability

Arasan’s ONFI 3.1 NAND Controller Total Solution including Controller IP core with DLL & PLL delivered in RTL, ONFI 3.1 I/O pads delivered in GDSII, and the optional ONFI 3.1 PHY with DLL & PLL delivered in GDSII are available now for shipment.