Communications
Jitter Attenuator with 250MHz Reference Clock
IDT has announced the introduction of a jitter attenuator optimized for the Xilinx Virtex-4 family of FPGAs. Designed to support PCI Express (PCIe), this component is said to be the industry’s first timing device capable of attenuating or “cleaning” the jitter from a 100 MHz PCIe input clock, while translating it to a 250 MHz LVDS output.
RemoThe ICS874003-02 is based on the industry-leading IDT FemtoClock technology, designed to cost-effectively generate reference clocks with extremely low, sub-1 picosecond RMS phase-noise to meet the stringent jitter requirements of PCIe-based communication applications.
The IDT PCI Express jitter attenuator is available in a RoHS-compliant 20-pin TSSOP package. An evaluation board is also available to aid the verification process.
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