IP Core performs a serial-to-parallel conversion

Reported status information includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). - The D16950 includes a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic – explains Jacek Hanke, DCD’s CEO.  Provisions are also included to use this n × clock to drive the receiver logic.

The D16950 UART IP Core is equipped with a complete MODEM-control capability and a processor-interrupt system. - Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link – adds Hanke. The D16950 core includes all other UARTs (16450, 16550, 16650 and 16750) features and additional functions. Saying this, one can mention the ICR registers, which give additional capabilities of UART work configuration. The data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register enables a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers, with any value set from 1 to 127.

DCD’s IP Core implements also auto flow control feature, which can significantly reduce software overload and automatically increase the system efficiency, by controlling serial data flow through the RTS output and the CTS input signals. The D16950 is perfect for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it's also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices.

Thanks to a universal interface, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. DCD’s IP Core includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. The D16950 is also a technology independent design, that can be implemented in a variety of process technologies.