IP core combines reduced CPU utilisation & low area consumption

A configurable IP Core, the DSMART is a configurable IP Core which can be easily adjusted to the project’s needs. Among proprietary options one can find, there is, for example, data transfer to and from the host system which can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result, no matter of the used convention. Elementary Time Unit (ETU) - time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies.

The IP Core also implements a special power down mode, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The device incorporates an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, so it can be read in case of CRC/LRC error. And, last but not least, the newest DCD’s IP Core provides optional block length counter to secure the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option.

Jacek Hanke, DCD’s CEO commented; "Small size, mobility and easy interaction with computers or other automated systems, create an instant demand for smart card systems. Immediate update of the stored data opens new markets for the smart card systems e.g. in healthcare (identification and patient authentication), banking (wireless payment), transportation (electronic ticketing) and many others"