High density mobile processor clusters handle Big Data

19th November 2014

IDT

Barney Scott

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Integrated Device Technology has announced the development of a compute architecture to handle the immense data demands of online gaming, high-performance computing and analytics, through high-density, low-latency clusters of connected mobile processors. Alongside Orange Silicon Valley, IDT co-developed a scalable cluster of low-power NVIDIA Tegra K1 processors, using IDT’s RapidIOinterconnect technology to connect nodes at up to 16Gb/s.

The architecture can scale to more than 2,000 nodes in a rack and enables ultra-high Gflop density and energy efficiency not achievable with PCI Express or Ethernet technologies. The result is a uniquely powerful force of computing horsepower built into very little board space.

With up to 23Tflops per 1U server, or greater than 800Tflops of computing per rack, the cluster architecture enables approximately twice the computing density of the world’s top supercomputer, Tianhe-2 in China. It achieves this by leveraging distributed switching and interconnect along with mobile-grade GPU technology, balancing I/O and compute per node in a best-in-class real estate footprint.

The architecture matches computing cores with 16Gb/s data rates to each node for better computing-to-throughput balance, one of the key limitations in the industry. The compute to I/O ratio will continue to improve with 40Gb/s IDT RapidIO 10xN technology.

The architecture allows for 60 nodes on a 19" 1U board. Any node can communicate with another node with only 400ns of fabric latency, and memory-to-memory latency is less than 2μs. Each node consists of a Tsi721 PCIe to RapidIO NIC and a Tegra K1 Mobile Processor with 384Gflops per 16Gb/s of data rate, or 24 floating point operations per bit of I/O. This will be valuable at the rack level in data centers and at the individual analytics server level for wireless access networks.

The cluster was achieved with NVIDIA’s Jetson TK1 development kit, powered by the NVIDIA Tegra K1 mobile processor. Built on the same NVIDIA Kepler GPU architecture that powers the world’s fastest supercomputers, Tegra K1 delivers 192 programmable CUDA cores for advanced graphics and compute performance.

“Leading innovators in the ‘Big Data’ arena are increasingly discovering the benefits that RapidIO interconnect can bring to their applications,” said Sean Fan, Vice President & General Manager, Interface and Connectivity Division, IDT. “Our work with Orange Silicon Valley - connecting massive numbers of low-power NVIDIA mobile processors via RapidIO - demonstrates a breakthrough approach to addressing the tradeoffs between total computing, power and balanced networking interconnect to feed the processors.”