FPGA industry’s first 56Gb/s PAM-4 & 30Gb/s NRZ transceivers

Stratix 10 FPGAs and SoCs are optimised to support the massive amounts of data that are being transmitted across copper backplanes and optical interconnects used in data centre infrastructure and telecomms equipment.

Altera has released the FPGA industry’s first dual-mode 56Gb/s PAM-4 and 30Gb/s NRZ transceivers.

The Stratix 10 FPGA transceiver technology will support data rates ranging from 1 to 56Gb/s. Customers can use Stratix 10 FPGAs to build next-gen communications and networking infrastructure that support 50G, 100G, 200G, 400G and terabit applications. The transceiver’s dual mode capabilities provide customers a path to develop next-gen high-end systems, while also providing investment protection by supporting mainstream and legacy backplanes, copper cables, chip-to-chip and chip-to-module interconnects and interfaces.

Jordon Inkeles, Director of Marketing, high-end products, Programmable Solutions Group, Intel, commented: “Today’s explosive growth in bandwidth requirements for data centres and network infrastructure requires that our FPGA’s power and density efficiently transmit more data, faster. As systems require data rates beyond 28Gb/s, traditional NRZ modulation schemes for data transmission are struggling to keep pace. The implementation of dual-mode 56Gb/s PAM-4 and 30Gb/s NRZ transceivers into our Stratix 10 FPGAs and SoCs will enable customers to address the most demanding data throughput requirements.”

Stratix 10 FPGA transceivers are integrated using a heterogeneous SiP approach. Transceiver tiles are combined with a monolithic FPGA core fabric using Intel’s embedded multi-die interconnect bridge technology, which allows Stratix 10 FPGAs and SoCs to rapidly address the ever-increasing system bandwidth demands across virtually every market segment. A transceiver tile approach offers greater flexibility, scalability and faster time-to-market.

Initial Stratix 10 FPGAs will start shipping in Q4 2016.