Communications
Faraday Launches Its USB 3.0 PHY in UMC 90nm
Faraday Technology Corporation today announced the availability of its commercial USB 3.0 physical layer (PHY) at UMC 90nm high-speed (HS) process. With smaller size and lower power consumption than peers', this new component is developed based upon USB 3.0 version 1.0 specification functionally and electrically, achieving the maximum speed of 5.0Gbps.
WithI am excited to announce the availability of our USB 3.0 PHY in 90 nm soon after the one in 0.13um, said Steve Wang, Chief Strategy Officer at Faraday. For the 0.13um version released in May, 2009, we have got market success in both host and device sides with mass production of mother board, express card, external HDD and flash storages. We believe the newly launched PHY in 90 nm with even lower power consumption and smaller die size can further assist our customers to implement their sophisticated SoC designs such as printer, surveillance, server and handheld applications, he added.
To achieve the target of low power design in 90nm, Faraday has carried out certain sophisticated improvement in the PHY architecture, including a regulated PLL structure to reduce design corners. Further, Faraday introduced a dual-loop half-rate structure for CDR and adopted the active peaking method to increase the effective bandwidth for transmitter to meet 5Gbps data rate with lower current consumption.
We are pleased to demonstrate our design capability by USB 3.0 in 90nm, said Y.K. Tseng, Associate Vice President at Faraday. We have accumulated a lot of experience in high-speed IO design and will continue to provide competitive solutions to our customers. UMC 0.11um aluminum and 55nm will be our next milestones with the hope of comprehensive USB 3.0 IP offerings to satisfy customers' demand in terms of cost competitiveness, stability, and performance. ”